DSPIC33FJ32GS608 datasheet(190/416 Pages) MICROCHIP

190 / 416 page

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610

DS70591B-page 190

Preliminary

 2009 Microchip Technology Inc.

TABLE 9-1:

CONFIGURATION BIT VALUES FOR CLOCK SELECTION

9.1.3

PLL CONFIGURATION

The primary oscillator and internal FRC oscillator can

optionally use an on-chip PLL to obtain higher speeds

of operation. The PLL provides significant flexibility in

selecting the device operating speed. A block diagram

of the PLL is shown in Figure 9-2.

The output of the primary oscillator or FRC, denoted as

‘FIN’, is divided down by a prescale factor (N1) of 2, 3,

... or 33 before being provided to the PLL’s Voltage

Controlled Oscillator (VCO). The input to the VCO must

be selected in the range of 0.8 MHz to 8 MHz. The

prescale

factor

‘N1’

selected

using

the

PLLPRE<4:0> bits (CLKDIV<4:0>).

The PLL Feedback Divisor, selected using the

PLLDIV<8:0> bits (PLLFBD<8:0>), provides a factor, ‘M’,

by which the input to the VCO is multiplied. This factor

must be selected such that the resulting VCO output

frequency is in the range of 100 MHz to 200 MHz.

The VCO output is further divided by a postscale factor,

‘N2’. This factor is selected using the PLLPOST<1:0>

bits (CLKDIV<7:6>). ‘N2’ can be either 2, 4 or 8, and

must be selected such that the PLL output frequency

(FOSC) is in the range of 12.5 MHz to 80 MHz, which

generates device operating speeds of 6.25-40 MIPS.

For a primary oscillator or FRC oscillator, output ‘FIN’,

the PLL output ‘FOSC’ is given by Equation 9-2.

EQUATION 9-2:

FOSC CALCULATION

For example, suppose a 10 MHz crystal is being used

with the selected oscillator mode of XT with PLL (see

Equation 9-3).

• If PLLPRE<4:0> = 0, then N1 = 2. This yields a

VCO input of 10/2 = 5 MHz, which is within the

acceptable range of 0.8-8 MHz.

• If PLLDIV<8:0> = 0x1E, then M = 32. This yields a

VCO output of 5 x 32 = 160 MHz, which is within

the 100-200 MHz ranged needed.

• If PLLPOST<1:0> = 0, then N2 = 2. This provides

a FOSC of 160/2 = 80 MHz. The resultant device

operating speed is 80/2 = 40 MIPS.

EQUATION 9-3:

XT WITH PLL MODE

EXAMPLE

Oscillator Mode

Oscillator Source POSCMD<1:0> FNOSC<2:0>

Note

Fast RC Oscillator with Divide-by-N (FRCDIVN)

Internal

111

1, 2

Fast RC Oscillator with Divide-by-16 (FRCDIV16)

Internal

110

Low-Power RC Oscillator (LPRC)

Internal

101

Secondary Oscillator (SOSC)

Secondary

100

—

Primary Oscillator (HS) with PLL (HSPLL)

Primary

011

—

Primary Oscillator (XT) with PLL (XTPLL)

Primary

011

—

Primary Oscillator (EC) with PLL (ECPLL)

Primary

011

Primary Oscillator (HS)

Primary

010

—

Primary Oscillator (XT)

Primary

010

—

Primary Oscillator (EC)

Primary

010

Fast RC Oscillator with PLL (FRCPLL)

Internal

001

Fast RC Oscillator (FRC)

Internal

000

Note 1:

OSC2 pin function is determined by the OSCIOFNC Configuration bit.

This is the default oscillator mode for an unprogrammed (erased) device.

(

)

N1*N2

FOSC = FIN *

FCY =

FOSC

2 (

10000000 * 32

2 * 2

) 40 MIPS

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