DSPIC33FJ32GS608 datasheet(187/416 Pages) MICROCHIP

187 / 416 page

 2009 Microchip Technology Inc.

Preliminary

DS70591B-page 187

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610

9.0

OSCILLATOR

CONFIGURATION

The

dsPIC33FJ32GS406/606/608/610

and

dsPIC33FJ64GS406/606/608/610 oscillator system

provides:

• External and internal oscillator options as clock

sources

• An on-chip Phase-Locked Loop (PLL) to scale the

internal operating frequency to the required

system clock frequency

• An internal FRC oscillator that can also be used with

the PLL, thereby allowing full-speed operation

without any external clock generation hardware

• Clock switching between various clock sources

• Programmable clock postscaler for system power

savings

• A Fail-Safe Clock Monitor (FSCM) that detects

clock failure and takes fail-safe measures

• A Clock Control register (OSCCON)

• Nonvolatile Configuration bits for main oscillator

selection.

• Auxiliary PLL for ADC and PWM

A simplified diagram of the oscillator system is shown

in Figure 9-1.

Note 1: This data sheet summarizes the features

of the dsPIC33FJ32GS406/606/608/610

and

dsPIC33FJ64GS406/606/608/610

families of devices. It is not intended to be

a comprehensive reference source. To

complement the information in this data

sheet, refer to Section 42. “Oscillator

(Part IV)” (DS70307) in the “dsPIC33F

Family Reference Manual”, which is

available from the Microchip web site

(www.microchip.com).

2: Some registers and associated bits

described in this section may not be avail-

able on all devices. Refer to Section 4.0

“Memory Organization” in this data

sheet for device-specific register and bit

information.

dsPIC33FJ32GS608 Datasheet(PDF) 187 Page - Microchip Technology

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