DSPIC33FJ32GS608 datasheet(191/416 Pages) MICROCHIP

191 / 416 page

 2009 Microchip Technology Inc.

Preliminary

DS70591B-page 191

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610

FIGURE 9-2:

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 PLL

BLOCK DIAGRAM

9.2

Auxiliary Clock Generation

The auxiliary clock generation is used for a peripherals

that need to operate at a frequency unrelated to the

system clock such as a PWM or ADC.

The primary oscillator and internal FRC oscillator

sources can be used with an auxiliary PLL to obtain the

auxiliary clock. The auxiliary PLL has a fixed 16x

multiplication factor.

9.3

Reference Clock Generation

The reference clock output logic provides the user with

the ability to output a clock signal based on the system

clock or the crystal oscillator on a device pin. The user

application can specify a wide range of clock scaling

prior to outputting the reference clock.

0.8-8.0 MHz

Here(1)

100-200 MHz

Here(1)

Divide by

2, 4, 8

Divide by

2-513

Divide by

2-33

Source (Crystal, External Clock

PLLPRE

XVCO

PLLDIV

PLLPOST

or Internal RC)

12.5-80 MHz

Here(1)

FOSC

Note 1: This frequency range must be satisfied at all times.

FVCO

Note:

To achieve 1.04 ns PWM resolution, the

auxiliary clock must be set up for 120 MHz.

Note:

If the primary PLL is used as a source for

the auxiliary clock, then the primary PLL

should be configured up to a maximum

operation of 30 MIPS or less.

dsPIC33FJ32GS608 Datasheet(PDF) 191 Page - Microchip Technology

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