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MCP1790-3302E/EB Datasheet(PDF) 15 Page - Microchip Technology |
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MCP1790-3302E/EB Datasheet(HTML) 15 Page - Microchip Technology |
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15 / 34 page ![]() © 2008 Microchip Technology Inc. DS22075A-page 15 MCP1790/MCP1791 4.5 Shutdown (SHDN) The MCP1791 has a Shutdown (SHDN) input signal that enables or disables the regulator output voltage. When the SHDN input signal is greater than 2.40V, the regulator output voltage is enabled. Note that the regulator output may still be disabled by the undervolt- age lockout incorporated within the VIN circuitry. The value of the SHDN signal to put the regulator into Shutdown mode is ≤ 0.8V. The SHDN pin is pulled low by an internal resistor. If the SHDN pin is left floating, the internal pull-down resistor will put the regulator into shutdown mode. When the SHDN input signal is pulled to a logic-low, the PWRGD output signal will also go low and the regulator will enter a low quiescent current state where the typi- cal quiescent current is 10 µA. There is a short time delay (approximately 400 ns) when the SHDN input signal transitions from high to low to prevent signal noise from disabling the regulator. The SHDN pin will ignore low-going pulses that are up to 400 ns in pulse width. If the SHDN input is pulled low for more than 400 ns, the regulator will enter Shutdown mode. This small bit of filtering helps to reject any system noise spikes on the SHDN input signal. On the rising edge of the SHDN input, the shutdown circuitry will have a 100 µs delay before allowing the regulator output to turn on. This delay helps to reject any false turn-on signals or noise on the SHDN input signal. After the 100 µs delay, the regulator will start charging the output capacitor as the regulator output voltage rises from 0V to its final regulated value. The charging current will be limited by the short circuit current value of the device. If the SHDN input signal is pulled low during the 100 µs delay period, the timer will be reset and the delay time will start over again on the next rising edge of the SHDN input. The total time from the SHDN input going high (turn-on) to the regulator output being in regulation shall typically be 200 µs (100 µs + 100 µs) for a CLOAD = 1.0 µF. FIGURE 4-2: Shutdown Input Timing Diagram. 4.6 Low Voltage Shutdown The MCP1790/MCP1791 incorporates a Low Voltage Shutdown circuit that turns off the output of the regula- tor whenever the input voltage, VIN, is below the specified turn off voltage, VOFF. When the input voltage (VB) drops below the differential needed to provide stable regulation, the output voltage (VREG) shall track the input down to approximately +4.00V. The regulator will turn off the output at this point. The output will turn on when VIN rises above the VON value specified in the data sheet. This feature is independent of the Shutdown input signal (SHDN) that is provided for external regulator control. If the SHDN input signal is active (LOW), then the output of the regulator shall be disabled regardless of input voltage. TABLE 4-1: SHUTDOWN LOGIC 4.7 Output Capacitor The MCP1790/MCP1791 requires a minimum output capacitance of 1 µF tantalum or electrolytic capaci- tance. The minimum value for ceramic capacitors is 4.7 µF. The regulator is stable for all three types of capacitors from 4.7 µF to 1000 µF (see Figure 4-3). The MCP1790/MCP1791 regulator may be used with a 1 µF ceramic output capacitor if a 0.300 Ω resistor is placed in series with the capacitor. The low ESR and corresponding pole of the ceramic capacitor causes the instability below 4.7 µF. The Equivalent Series Resistance (ESR) of the output capacitor must be no greater than 3 ohms. The output capacitor should be located as close to the regulator output as is practical. Ceramic materials X7R and X5R have low temperature coefficients and are recommended because of their size, cost, and environmental robustness qualities. SHDN VOUT 100 µs 100 µs TOR 400 ns (typ) CLOAD = 1.0 µF CLOAD CHARGING TIME VIN SHDN VOUT < VOFF LOFF < VOFF HOFF > VON LOFF > VON HON |
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