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PIC12F609-E/P Datasheet(PDF) 157 Page - Microchip Technology

Part # PIC12F609-E/P
Description  8-Pin, Flash-Based 8-Bit CMOS Microcontrollers
PDF  212 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC12F609-E/P Datasheet(HTML) 157 Page - Microchip Technology

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 2010 Microchip Technology Inc.
DS41302D-page 157
PIC12F609/615/617/12HV609/615
TABLE 16-2:
OSCILLATOR PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature
-40°C
TA +125°C
Param
No.
Sym
Characteristic
Freq.
Tolerance
Min
Typ†
Max
Units
Conditions
OS06
TWARM
Internal Oscillator Switch
when running(3)
——
—
2
TOSC
Slowest clock
OS07
INTOSC
Internal Calibrated
INTOSC Frequency(2)
(4MHz)
1%
3.96
4.0
4.04
MHz
VDD = 3.5V, TA = 25°C
2%
3.92
4.0
4.08
MHz
2.5V
VDD  5.5V,
0°C
 TA  +85°C
5%
3.80
4.0
4.2
MHz
2.0V
VDD  5.5V,
-40°C
 TA  +85°C (Ind.),
-40°C
 TA  +125°C (Ext.)
OS08
INTOSC
Internal Calibrated
INTOSC Frequency(2)
(8MHz)
1%
7.92
8.0
8.08
MHz
VDD = 3.5V, TA = 25°C
2%
7.84
8.0
8.16
MHz
2.5V
VDD  5.5V,
0°C
 TA  +85°C
5%
7.60
8.0
8.40
MHz
2.0V
VDD  5.5V,
-40°C
 TA  +85°C (Ind.),
-40°C
 TA  +125°C (Ext.)
OS10*
TIOSC ST
INTOSC Oscillator Wake-
up from Sleep
Start-up Time
—
5.5
12
24
sVDD = 2.0V, -40°C to +85°C
—3.5
7
14
sVDD = 3.0V, -40°C to +85°C
—3
6
11
sVDD = 5.0V, -40°C to +85°C
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note
1:
Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing
code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected
current consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin.
When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
2:
To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1
F and 0.01 F values in parallel are recommended.
3:
By design.



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