LTC2471CDD datasheet(15/20 Pages) LINER

15 / 20 page

LTC2471/LTC2473

24713f

APPLICATIONS INFORMATION

0.1μF capacitors are used. The ﬁrst conversion following

power up can be discarded using the data abort com-

mand or simply read and ignored. Depending on the value

chosen for CCOMP and CREFOUT, the reference startup can

take more than one conversion period, see Figure 3. If

the startup time is less than 1ms (1ksps output rate) or

4ms (250sps output rate) then conversions following the

ﬁrst period are accurate to the device speciﬁcations. If the

startup time exceeds 1ms or 4ms then the user can wait

the appropriate time or use the ﬁxed conversion period

as a startup timer by ignoring results within the unsettled

period. Once the reference has settled all subsequent

conversion results are valid. If the user places the device

into the sleep mode (SLP = 1, reference powered down)

the reference will require a startup time proportional to

the value of CCOMP and CREFOUT, see Figure 3.

If the reference is put to sleep (program SLP = 1 and CS =

1) the reference is powered down after the next conversion.

This last conversion result is valid. On CS falling edge,

the reference is powered back up. In order to ensure the

reference output has settled before the next conversion,

the power up time can be extended by delaying the data

read after the falling edge of CS. Once all 16 bits are read

from the device or CS is brought HIGH, the next conver-

sion automatically begins. In the default operation, the

reference remains powered up at the conclusion of the

conversion cycle.

Driving VIN+ and VIN–

The input drive requirements can best be analyzed using

the equivalent circuit of Figure 12. The input signal VSIG is

connected to the ADC input pins (IN+ and IN–) through an

equivalent source resistance RS.Thisresistorincludesboth

the actual generator source resistance and any additional

optional resistors connected to the input pins. Optional

input capacitors CIN are also connected to the ADC input

pins. This capacitor is placed in parallel with the input

parasitic capacitance CPAR. This parasitic capacitance

includes elements from the printed circuit board (PCB)

and the associated input pin of the ADC. Depending on the

PCB layout, CPAR has typical values between 2pF and 15pF.

In addition, the equivalent circuit of Figure 12 includes the

converter equivalent internal resistor RSW and sampling

capacitor CEQ.

There are some immediate trade-offs in RS and CIN without

needing a full circuit analysis. Increasing RS and CIN can

give the following beneﬁts:

1) Due to the LTC2471/LTC2473’s input sampling algo-

rithm, the input current drawn by either IN+ or IN– over

a conversion cycle is typically 50nA. A high RS • CIN

attenuates the high frequency components of the input

current, and RS values up to 1k result in <1LSB error.

2) The bandwidth from VSIG is reduced at the input pins

(IN+, IN– or IN). This bandwidth reduction isolates the

ADC from high frequency signals, and as such provides

simple anti-aliasing and input noise reduction.

3) Switching transients generated by the ADC are attenu-

ated before they go back to the signal source.

4) A large CIN gives a better AC ground at the input pins,

helping reduce reﬂections back to the signal source.

5) Increasing RS protects the ADC by limiting the current

during an outside-the-rails fault condition.

Figure 12. LTC2471/LTC2473 Input Drive Equivalent Circuit

ILEAK

RSW

15k

(TYP)

ICONV

CIN

IN+

(LTC2473)

(LTC2471)

VCC

SIG+

SIG–

CEQ

0.35pF

(TYP)

CPAR

–

24713 F12

ILEAK

RSW

15k

(TYP)

ICONV

CIN

IN–

(LTC2473)

VCC

CEQ

0.35pF

(TYP)

CPAR

–

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