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VG37648041AT Datasheet(PDF) 59 Page - Vanguard International Semiconductor |
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VG37648041AT Datasheet(HTML) 59 Page - Vanguard International Semiconductor |
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59 / 86 page  Document : 1G5-0157 Rev.1 Page 59 VIS Preliminary VG37648041AT 256M:x4, x8, x16 CMOS Synchronous Dynamic RAM Dl b=Data In for column b An interrupted burst of 4 or 8 is shown, 2 data elements are written 1 subsequent element of Data In is applied in the programmed order following Dl b tWR is referenced from the first positive CLK edge after the last desired Data In pair A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled) *1=can be don’t care for programmed burst length of 4 *2=for programmed burst length of 4, DQS becomes don’t care at this point DON’T CARE UNDEFINED CLK# CLK COMMAND ADDRESS WRITE NOP NOP NOP PRE NOP Col b Bank a, Figure 33 WRITE TO PRECHARGE - NOMINAL DSS, INTERRUPTING DQS Bank, (a or all) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 DM DQ tDSS nom tWR tRP *2 *1 *1 *1 Dl b |
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