Preliminary and proprietary Information of YAMAR Electronics Ltd. Subject to change without notice.

© 2010 Yamar Electronics Ltd.

3

DS-SIG61 R0.932

3 SIG61 SIGNALS

Device signals are described in table 3.1.

SIG61

DTxO

45

In2_HDI

42

HDO

35

In3_HDC

41

F1nF0

38

InterHope

3

Test

15

Gnd

46

TxO

8

Gnd

6

BitRate0

1

RxIn

10

Vdd

4

RxN

9

In0

47

In1

44

In6

37

In4

40

In5

39

In7

36

Id0

16

Id1

14

Id2

13

Id3

12

Vdd

34

Gnd

33

Mode2_LBD

48

Vdd

43

NC

5

BitRate1

2

Gnd

7

Vdd

11

EXP

EXP

Pin name

Pin# Pin type

Description

Control Signals

HDO

35

Output

8mA

Digital data output signal. Output the received data from the

powerline to the host.

INH

32

Output

8mA

Inhibit output for enabling the host or an external voltage regulator

powering the host. This signal is HIGH in the normal and standby

modes and LOW in sleep mode.

nSleep

31

Input

Sleep control input. Pulling this signal to LOW puts the SIG61 in

sleep mode. Should be pulled to Vdd.

Wake

26

Input

Local wakeup input. Negative or positive edge triggered. This pin can

be connected to an external switch in the application. When the pin is

triggered the device will wake up and send a wake up message to all

the devices on the network. When not in use, this pin should be

pulled Up or Down.

nReset

29

Input, PU Reset Input

InterfHop

3

is detected on the DC line. When HIGH, detection of interference

switches the operating frequency between F0 and F1. If at the new

frequency, no reception occurred for 2 sec, the operating frequency is

switched back. For designs with a single channel this pin should be

tied to ground.

Test

15

Input, PD Should be connected to Gnd

MF1nF0

23

Output

12mA

Output indicating the operating frequency. F1 when HIGH and F0

when LOW.

Line Interface signals

OscO

52

Analog

Output

Crystal Output

Figure 3.1 - SIG61 Pin-out