PCF2127ATSLASH1 datasheet(36/80 Pages) NXP

36 / 80 page

PCF2127A_2

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Product data sheet

Rev. 02 — 7 May 2010

36 of 80

NXP Semiconductors

PCF2127A

Integrated RTC, TCXO and quartz crystal

8.11.2 Register Watchdg_tim_val

8.11.3 Watchdog timer function

The watchdog timer function is controlled by the WD_CD[1:0] bits of the register

Watchdg_tim_ctl (see Table 34).

The two bits TF[1:0] in register Watchdg_tim_ctl determine one of the four source clock

frequencies for the watchdog timer: 4.096 kHz, 64 Hz, 1 Hz, or 1

⁄

60 Hz (see Table 36).

When the watchdog timer function is enabled, the 8 bit timer in register Watchdg_tim_val

(see Table 35) determines the watchdog timer period.

The watchdog timer counts down from the software programmed 8 bit binary value n in

(register Control_2) is set logic 1.

In the case that WDTF is logic 1:

• if WD_CD[1:0] = 10 an interrupt will be generated

• if WD_CD[1:0] = 11 a reset will be generated

The counter does not automatically reload.

When WD_CD[1:0] = 10 or WD_CD[1:0] = 11 and the microcontroller unit (MCU) loads a

watchdog timer value n:

• the flag WDTF is reset

• INT or RST is cleared

• the watchdog timer starts again

Loading the counter with 0 will:

• reset the flag WDTF

• clear INT or RST

• stop the watchdog timer

Table 35.

Watchdg_tim_val - watchdog timer value register (address 11h) bit description

Bit

Symbol

Value

Description

7 to 0 WATCHDG_TIM_VAL[7:0]

00 to FF

countdown period in seconds:

where n is the countdown value

Table 36.

Programmable watchdog or countdown timer

TF[1:0]

Timer source

clock frequency

Units

Minimum timer

period (n = 1)

Units

Maximum timer

period (n = 255)

Units

4.096

kHz

244

μs

62.256

15.625

3.984

255

⁄

15300

CountdownPeriod

SourceClockFrequency

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