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PCF2127AT/1 Datasheet(PDF) 38 Page - NXP Semiconductors

Part # PCF2127AT/1
Description  Integrated RTC, TCXO and quartz crystal
PDF  80 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

PCF2127AT/1 Datasheet(HTML) 38 Page - NXP Semiconductors

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PCF2127A_2
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 7 May 2010
38 of 80
NXP Semiconductors
PCF2127A
Integrated RTC, TCXO and quartz crystal
8.11.4 Countdown timer function
The countdown timer function is controlled by the WD_CD[1:0] bits in register
Watchdg_tim_ctl (see Table 34).
The timer counts down from the software programmed 8 bit binary value n in register
Watchdg_tim_val. When the counter reaches 1
• the countdown timer flag CDTF is set
• the counter automatically reloads
• and the next time period starts
Loading the counter with 0 effectively stops the timer.
Reading the timer will return the actual value of the countdown counter.
If a new value of n is written before the end of the actual timer period, this value will take
immediate effect. It is not recommended to change n without first disabling the counter by
setting WD_CD[1:0] = 00. The update of n is asynchronous to the timer clock. Therefore
changing it on the fly could result in a corrupted value loaded into the countdown counter.
This can result in an undetermined countdown period for the first period. The countdown
value n will, however, be correctly stored and correctly loaded on subsequent timer
periods.
Table 37.
Specification of tw(rst)
WD_CD[1:0]
TF[1:0]
tw(rst)
11
00
244
μs
01
15.625 ms
10
15.625 ms
11
15.625 ms
In this example it is assumed that the countdown timer flag (CDTF) is cleared before the next
countdown period expires and that INT is set to pulsed mode.
Fig 23. General countdown timer behavior
001aag071
countdown value, n
timer source clock
countdown counter
WD/CD [1:0]
CDTF
INT
02
03
00
01
XX
03
XX
01
03
02
01
03
02
n
duration of first timer period after
enable may range from n
−1 to n+1
n
01
03



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