PCF2127ATSLASH1 datasheet(59/80 Pages) NXP

59 / 80 page

PCF2127A_2

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Product data sheet

Rev. 02 — 7 May 2010

59 of 80

NXP Semiconductors

PCF2127A

Integrated RTC, TCXO and quartz crystal

The R/W bit defines the direction of the following single or multiple byte data transfer (read

is logic 1, write is logic 0).

For the format and the timing of the START condition (S), the STOP condition (P), and the

acknowledge bit (A) refer to the I2C-bus specification Ref. 13 “UM10204” and the

characteristics table (Table 64). In the write mode a data transfer is terminated by sending

either a STOP condition or the START condition of the next data transfer.

Table 59.

I2C slave address byte

Slave address

Bit

MSB

LSB

1R/W

Fig 42. Bus protocol, writing to registers

001aaj719

slave address

00h to 1Dh

0 to n

data bytes

write bit

START/

STOP

acknowledge

from PCF2127A

acknowledge

from PCF2127A

acknowledge

from PCF2127A

P/S

Fig 43. Bus protocol, reading from registers

001aaj721

slave address

0 to n data bytes

DATA BYTE

LAST DATA BYTE

read bit

acknowledge

from PCF2127A

acknowledge

from master

no acknowledge

slave address

00h to 1Dh

set register

address

read register

data

write bit

STOP

acknowledge

from PCF2127A

acknowledge

from PCF2127A

PCF2127AT/1 Datasheet(PDF) 59 Page - NXP Semiconductors

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