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HT82K75REW Datasheet(PDF) 56 Page - Holtek Semiconductor Inc |
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HT82K75REW Datasheet(HTML) 56 Page - Holtek Semiconductor Inc |
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56 / 103 page  HT82M75REW/HT82K75REW Rev. 1.00 56 June 11, 2010 ¨ SPI Addressing Format MSB of addressing frame indicates the addressing mode of the packet. The length of address field is 6 or 10 bits for short and long addressing mode respectively. Bit 0 is a one-bit read/write indicator. ¨ SPI Characteristics Parameter Symbol Min. Max. Unit Conditions SCLK, clock frequency fSCLK ¾ 5 MHz SCLK low pulse duration tCL 100 ¾ ns The minimum time SCLK must be low. SCLK high pulse duration tCH 100 ¾ ns The minimum time SCLK must be high. SEN setup time tSP 100 ¾ ns The minimum time SEN must be low before the first positive edge of SCLK. SEN hold time tNS 100 ¾ ns The minimum time SEN must be held low after the last negative edge of SCLK. SI setup tSD 25 ¾ ns The minimum time data must be ready at SI, before the positive edge of SCLK SI hold time tHD 25 ¾ ns The minimum time data must be held at SI, after the positive edge of SCLK. Rise time tRISE ¾ 25 ns The maximum rise time for SCLK and SEN. Fall time tFALL ¾ 25 ns The maximum fall time for SCLK and SEN. ¨ SPI Timing Diagram The following figures show the timing diagrams for the short and long addressing mode respectively. The MCU SPI master will initiate a read or write operation by asserting the interface enable signal SEN to low, toggling SCLK and sent the address field by SI. The interface enable signal SEN should be high when a transaction is completed. SPI Addressing Format A6 A5 A3 A4 A2 A1 0 0 DR7DR6 DR4 DR5 DR3DR2 DR0 DR1 0 A6 X A6 A5 A3 A4 A2 A1 1 0 Dw6 Dw4 Dw5 Dw3Dw2 Dw0 Dw1 0 Dw7 SCLK SEN SI SO SI SO tSP tSD tHD tCH tCL tNS read short address data writeshort addressdata A5 A4 A3 A2 A1 0 X DR7 DR5 DR6 A6 A5 A3 A4 A2 A1 1 Dw6 Dw5 Dw7 Timing Diagram of Short Addressing Mode |
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