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PIC16F707-E/ML Datasheet(PDF) 61 Page - Microchip Technology

Part # PIC16F707-E/ML
Description  40/44-Pin, Flash Microcontrollers with nanoWatt XLP and mTouch??Technology
PDF  284 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC16F707-E/ML Datasheet(HTML) 61 Page - Microchip Technology

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 2010 Microchip Technology Inc.
Preliminary
DS41418A-page 61
PIC16F707/PIC16LF707
6.4.2.3
RC2/CCP1/CPSB4/TBCKI
These pins are configurable to function as one of the
following:
• General purpose I/O
• Capture 1 input, Compare 1 output, and PWM1
output
• Capacitive sensing input
• TimerB Clock input
6.4.2.4
RC3/SCK/SCL
These pins are configurable to function as one of the
following:
• General purpose I/O
• SPI clock
•I2C™ clock
6.4.2.5
RC4/SDI/SDA
These pins are configurable to function as one of the
following:
• General purpose I/O
• SPI data input
•I2C data I/O
6.4.2.6
RC5/SDO/CPSA9
These pins are configurable to function as one of the
following:
• General purpose I/O
• SPI data output
• Capacitive sensing input
6.4.2.7
RC6/TX/CK/CPSA10
These pins are configurable to function as one of the
following:
• General purpose I/O
• Asynchronous serial output
• Synchronous clock I/O
• Capacitive sensing input
6.4.2.8
RC7/RX/DT/CPSA11
These pins are configurable to function as one of the
following:
• General purpose I/O
• Asynchronous serial input
• Synchronous serial data I/O
• Capacitive sensing input
TABLE 6-3:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
ANSELC
ANSC7
ANSC6
ANSC5
—
—
ANSC2
ANSC1
ANSC0
111- -111
111- -111
APFCON
—
—
—
—
—
—
SSSEL
CCP2SEL
---- --00
---- --00
CCP1CON
—
—
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
--00 0000
--00 0000
CCP2CON
—
—
DC2B1
DC2B0
CCP2M3
CCP2M2
CCP2M1
CCP2M0
--00 0000
--00 0000
CPSACON0
CPSAON
CPSARM
—
—
CPSARNG1 CPSARNG0 CPSAOUT
TAXCS
00-- 0000
00-- 0000
CPSACON1
—
—
—
—
CPSACH3
CPSACH2
CPSACH1 CPSACH0 ---- 0000
---- 0000
CPSBCON0
CPSBON
CPSBRM
—
—
CPSBRNG1 CPSBRNG0 CPSBOUT
TBXCS
00-- 0000
00-- 0000
CPSBCON1
—
—
—
—
CPSBCH3
CPSBCH2
CPSBCH1 CPSBCH0 ---- 0000
---- 0000
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx
xxxx xxxx
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
0000 000x
SSPCON
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000
0000 0000
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000
0000 0000
T1CON
TMR1CS1
TMR1CS0
T1CKPS1 T1CKPS0
T1OSCEN
T1SYNC
—
TMR1ON
0000 00-0
uuuu uu-u
TBCON
TMRBON
—
TBCS
TBSE
TBPSA
TBPS2
TBPS1
TBPS0
0-00 0000
0-00 0000
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010
0000 -010
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
1111 1111
Legend:
x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.



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