PIC16F707-ESLASHML datasheet(104/284 Pages) MICROCHIP

104 / 284 page

PIC16F707/PIC16LF707

DS41418A-page 104

Preliminary

 2010 Microchip Technology Inc.

13.6.7

TIMER1/3 GATE TOGGLE MODE

When Timer1/3 Gate Toggle mode is enabled, it is

possible to measure the full-cycle length of a Timer1/3

gate signal, as opposed to the duration of a single level

pulse.

The Timer1/3 gate source is routed through a flip-flop

that changes state on every incrementing edge of the

signal. See Figure 13-4 for timing details.

Timer1/3 Gate Toggle mode is enabled by setting the

TxGTM bit of the TxGCON register. When the TxGTM

bit is cleared, the flip-flop is cleared and held clear. This

is necessary in order to control which edge is

measured.

13.6.8

TIMER1/3 GATE SINGLE-PULSE

MODE

When Timer1/3 Gate Single-Pulse mode is enabled, it

is possible to capture a single pulse gate event.

Timer1/3 Gate Single-Pulse mode is first enabled by

setting the TxGSPM bit in the TxGCON register. Next,

the TxGGO/DONE bit in the TxGCON register must be

set. The Timer1/3 will be fully enabled on the next

incrementing edge. On the next trailing edge of the

pulse, the TxGGO/DONE bit will automatically be

cleared. No other gate events will be allowed to incre-

ment Timer1/3 until the TxGGO/DONE bit is once

again set in software.

Clearing the TxGSPM bit of the TxGCON register will

also clear the TxGGO/DONE bit. See Figure 13-5 for

timing details.

Enabling the Toggle mode and the Single-Pulse mode

simultaneously will permit both sections to work

together. This allows the cycle times on the Timer1/3

gate source to be measured. See Figure 13-6 for timing

details.

13.6.9

TIMER1/3 GATE VALUE STATUS

When Timer1/3 gate value status is utilized, it is

possible to read the most current level of the gate

control value. The value is stored in the TxGVAL bit in

the TxGCON register. The TxGVAL bit is valid even

when the Timer1/3 gate is not enabled (TMRxGE bit is

cleared).

13.6.10

TIMER1/3 GATE EVENT

INTERRUPT

When Timer1/3 gate event interrupt is enabled, it is

possible to generate an interrupt upon the completion

of a gate event. When the falling edge of TxGVAL

occurs, the TMRxGIF flag bit in the PIRx register will be

set. If the TMRxGIE bit in the PIEx register is set, then

an interrupt will be recognized. See Table 13-7 for

interrupt bit locations.

The TMRxGIF flag bit operates even when the

Timer1/3 gate is not enabled (TMRxGE bit is cleared).

13.7

Timer1/3 Interrupt

The

Timer1/3

pair

(TMRxH:TMRxL)

increments to FFFFh and rolls over to 0000h. When

Timer1/3 rolls over, the Timer1/3 interrupt flag bit of the

PIRx register is set. See Table 13-7 for interrupt bit

locations.

To enable the interrupt on rollover, you must set these

bits:

• TMRxON bit of the TxCON register

• TMRxIE bit of the PIEx register

• PEIE bit of the INTCON register

• GIE bit of the INTCON register

The interrupt is cleared by clearing the TMRxIF bit in

the Interrupt Service Routine.

Note:

Enabling Toggle mode at the same time

as changing the gate polarity may result in

indeterminate operation.

TABLE 13-7:

TIMER1/3 INTERRUPT BIT LOCATIONS

Timer1

Timer3

Interrupt Flag

TMR1IF bit in PIR1 register

TMR3IF bit in PIR2 register

Interrupt Enable

TMR1IE bit in PIE1 register

TMR3IE bit in PIE2 register

Gate Interrupt Flag

TMR1GIF bit in PIR1 register

TMR3GIF bit in PIR2 register

Gate Interrupt Enable

TMR1GIE bit in PIE1 register

TMR3GIE bit in PIE2 register

Note:

The TMRxH:TMRxL register pair and the

TMRxIF bit should be cleared before

enabling interrupts.

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