 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
PIC16F707-E/ML Datasheet(PDF) 184 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
PIC16F707-E/ML Datasheet(HTML) 184 Page - Microchip Technology |
|
|
184 / 284 page  PIC16F707/PIC16LF707 DS41418A-page 184 Preliminary 2010 Microchip Technology Inc. 21.1.1 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: • If the interrupt occurs before the execution of a SLEEP instruction - SLEEP instruction will execute as a NOP. - WDT and WDT prescaler will not be cleared -TO bit of the STATUS register will not be set -PD bit of the STATUS register will not be cleared. • If the interrupt occurs during or after the execu- tion of a SLEEP instruction - SLEEP instruction will be completely exe- cuted - Device will immediately wake-up from Sleep - WDT and WDT prescaler will be cleared -TO bit of the STATUS register will be set -PD bit of the STATUS register will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. FIGURE 21-1: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1(1) CLKOUT(2) Interrupt flag GIE bit (INTCON reg.) Instruction Flow PC Instruction Fetched Instruction Executed PC PC + 1 PC + 2 Inst(PC) = Sleep Inst(PC - 1) Inst(PC + 1) Sleep Processor in Sleep Interrupt Latency(4) Inst(PC + 2) Inst(PC + 1) Inst(0004h) Inst(0005h) Inst(0004h) Dummy Cycle PC + 2 0004h 0005h Dummy Cycle TOST(3) PC + 2 Note 1: XT, HS or LP Oscillator mode assumed. 2: CLKOUT is not available in XT, HS, or LP Oscillator modes, but shown here for timing reference. 3: TOST = 1024 TOSC (drawing not to scale). This delay applies only to XT, HS or LP Oscillator modes. 4: GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line. TABLE 21-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000x IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4IOCBF3IOCBF2IOCBF1 IOCBF0 0000 0000 0000 0000 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 PIE2 TMR3GIE TMR3IE TMRBIE TMRAIE — — — CCP2IE 0000 ---0 0000 ---0 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIR2 TMR3GIF TMR3IF TMRBIF TMRAIF — — — CCP2IF 0000 ---0 0000 ---0 STATUS IRP RP1 RP0 TO PD ZDC C 0001 1xxx 000q quuu Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used in Power-down mode. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
New Zealand ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
