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PIC16F1826-E/ML Datasheet(PDF) 121 Page - Microchip Technology |
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PIC16F1826-E/ML Datasheet(HTML) 121 Page - Microchip Technology |
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121 / 406 page  2010 Microchip Technology Inc. Preliminary DS41391C-page 121 PIC16F/LF1826/27 12.0 I/O PORTS Depending on the device selected and peripherals enabled, there are two ports available. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has three registers for its operation. These registers are: • TRISx registers (data direction register) • PORTx registers (reads the levels on the pins of the device) • LATx registers (output latch) The Data Latch (LATx registers) is useful for read-modify-write operations on the value that the I/O pins are driving. A write operation to the LATx register has the same affect as a write to the corresponding PORTx register. A read of the LATx register reads of the values held in the I/O PORT latches, while a read of the PORTx register reads the actual I/O pin value. Ports with analog functions also have an ANSELx register which can disable the digital input and save power. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure 12-1. FIGURE 12-1: GENERIC I/O PORT OPERATION 12.1 Alternate Pin Function The Alternate Pin Function Control (APFCON0 and APFCON1) registers are used to steer specific peripheral input and output functions between different pins. The APFCON0 and APFCON1 registers are shown in Register 12-1 and Register 12-2. For this device family, the following functions can be moved between different pins. •RX/DT •SDO1 •SS1 (Slave Select 1) •P2B • CCP2/P2A •P1D •P1C • CCP1/P1A •TX/CK These bits have no effect on the values of any TRIS register. PORT and TRIS overrides will be routed to the correct pin. The unselected pin will be unaffected. Q D CK Write LATx Data Register I/O pin Read PORTx Write PORTx TRISx Read LATx Data Bus To peripherals ANSELx VDD VSS |
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