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PIC18F14K22-E/ML Datasheet(PDF) 40 Page - Microchip Technology |
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PIC18F14K22-E/ML Datasheet(HTML) 40 Page - Microchip Technology |
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40 / 388 page  PIC18F1XK22/LF1XK22 DS41365D-page 40 Preliminary 2010 Microchip Technology Inc. TMR0H Timer0 Register, High Byte 0000 0000 258, 98 TMR0L Timer0 Register, Low Byte xxxx xxxx 258, 98 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 258, 97 OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS HFIOFS SCS1 SCS0 0011 qq00 258, 20 OSCCON2 — — — — — PRI_SD HFIOFL LFIOFS ---- -10x 258, 21 WDTCON — — — — — — —SWDTEN --- ---0 258, 272 RCON IPEN SBOREN(1) —RI TO PD POR BOR 0q-1 11q0 249, 256, 67 TMR1H Timer1 Register, High Byte xxxx xxxx 258, 101 TMR1L Timer1 Register, Low Bytes xxxx xxxx 258, 101 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 258, 101 TMR2 Timer2 Register 0000 0000 258, 107 PR2 Timer2 Period Register 1111 1111 258, 107 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 258, 107 SSPBUF SSP Receive Buffer/Transmit Register xxxx xxxx 258, 136, 138 SSPADD SSP Address Register in I2C™ Slave Mode. SSP Baud Rate Reload Register in I2C Master Mode. 0000 0000 258, 155 SSPSTAT SMP CKE D/A PS R/W UA BF 0000 0000 258, 136, 145 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 258, 136, 146 SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 258, 147 ADRESH A/D Result Register, High Byte xxxx xxxx 259, 207 ADRESL A/D Result Register, Low Byte xxxx xxxx 259, 207 ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 259, 213 ADCON1 — — — — PVCFG1 PVCFG0 NVCFG1 NVCFG0 ---- 0000 259, 214 ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 259, 215 CCPR1H Capture/Compare/PWM Register 1, High Byte xxxx xxxx 259, 133 CCPR1L Capture/Compare/PWM Register 1, Low Byte xxxx xxxx 259, 133 CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 259, 113 VREFCON2 — — — DAC1R4 DAC1R3 DAC1R2 DAC1R1 DAC1R0 ---0 0000 259, 246 VREFCON1 D1EN D1LPS DAC1OE --- D1PSS1 D1PSS0 — D1NSS 000- 00-0 259, 246 VREFCON0 FVR1EN FVR1ST FVR1S1 FVR1S0 — — — — 0001 ---- 259, 245 PSTRCON — — — STRSYNC STRD STRC STRB STRA ---0 0001 259, 130 BAUDCON ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 0100 0-00 259, 190 PWM1CON PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 259, 129 ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 259, 125 TMR3H Timer3 Register, High Byte xxxx xxxx 259, 109 TMR3L Timer3 Register, Low Byte xxxx xxxx 259, 109 T3CON RD16 — T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0-00 0000 259, 109 TABLE 3-2: REGISTER FILE SUMMARY (PIC18F1XK22/LF1XK22) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition Note 1: The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise it is disabled and reads as ‘0’. See Section 21.4 “Brown-out Reset (BOR)”. 2: The RA3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0). Otherwise, RA3 reads as ‘0’. This bit is read-only. |
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