PIC18F14K22-ESLASHML datasheet(83/388 Pages) MICROCHIP

83 / 388 page

 2010 Microchip Technology Inc.

Preliminary

DS41365D-page 83

PIC18F1XK22/LF1XK22

TABLE 8-1:

PORTA I/O SUMMARY

Function

TRIS

Setting

I/O

Type

Description

RA0/AN0/CVREF/

VREF-/C1IN+/INT0/

PGD

RA0

DIG

LATA<0> data output.

TTL

PORTA<0> data input; Programmable weak pull-up.

AN0

ANA

ADC channel 0 input.

CVREF

ANA

Comparator reference voltage output.

VREF-

ANA

ADC and Comparator voltage reference voltage (low) input.

C1IN+

DIG

Comparator C1 non-inverting input.

INT0

External interrupt 0.

PGD

DIG

Serial execution data output for ICSP™.

Serial execution data input for ICSP™.

RA1/AN1/C12IN0-/

VREF+/INT1/PGC

RA1

DIG

LATA<1> data output.

TTL

PORTA<1> data input; Programmable weak pull-up.

AN1

ANA

ADC channel 1.

C12IN0-

ANA

Comparator C1 and C2 non-inverting input channel 0.

VREF+

ANA

Comparator reference voltage (high) input ADC qual.

INT1

External interrupt 1.

PGC

DIG

Serial execution clock output for ICSP™.

Serial execution clock input for ICSP™.

RA2/AN2/C1OUT/

T0CKI/INT2/SRQ

RA2

DIG

LATA<2> data output.

TTL

PORTA<2> data input; Programmable weak pull-up.

AN2

ANA

ADC channel 2.

C1OUT

DIG

Comparator C1 output.

T0CKI

Timer0 external clock input.

INT2

External interrupt 2.

SRQ

DIG

SR latch output.

RA3/MCLR/VPP

RA3

—(1)

IST

PORTA<37> data input; Programmable weak pull-up.

MCLR

—I

Active-low Master Clear with internal pull-up.

VPP

—I

ANA

High voltage programming input.

RA4/AN3/OSC2/

CLKOUT

RA4

DIG

LATA<4> data output.

TTL

PORTA<4> data input; Programmable weak pull-up.

AN3

IANA

A/D input channel 3.

OSC2

OANA

Main oscillator feedback output connection (XT, HS and LP modes).

CLKOUT

ODIG

System instruction cycle clock output.

RA5/OSC1/CLKIN/

T13CKI

RA5

DIG

LATA<5> data output.

TTL

PORTA<5> data input; Programmable weak pull-up.

OSC1

ANA

Main oscillator input connection.

CLKIN

ANA

Main clock input connection.

T13CKI

IST

Timer1 and Timer3 external clock input.

Legend:

DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;

x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).

Note 1: RA3 does not have a corresponding TRISA bit. This pin is always an input regardless of mode.

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