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PIC18F23K20-E/ML Datasheet(PDF) 446 Page - Microchip Technology |
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PIC18F23K20-E/ML Datasheet(HTML) 446 Page - Microchip Technology |
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446 / 456 page  PIC18F2XK20/4XK20 DS41303G-page 446 2010 Microchip Technology Inc. Synchronous Mode .......................................... 257 Interrupts Asychronous Receive ...................................... 243 Asychronous Transmit ..................................... 239 Synchronous Master Mode .............................. 257, 262 Associated Registers, Receive ........................ 261 Associated Registers, Transmit ............... 259, 262 Reception ......................................................... 260 Transmission .................................................... 257 Synchronous Slave Mode Associated Registers, Receive ........................ 263 Reception ......................................................... 263 Transmission .................................................... 262 Extended Instruction Set ADDFSR .................................................................. 358 ADDULNK ................................................................ 358 and Using MPLAB Tools .......................................... 364 CALLW ..................................................................... 359 Considerations for Use ............................................ 362 MOVSF .................................................................... 359 MOVSS .................................................................... 360 PUSHL ..................................................................... 360 SUBFSR .................................................................. 361 SUBULNK ................................................................ 361 Syntax ...................................................................... 357 F Fail-Safe Clock Monitor .............................................. 40, 299 Fail-Safe Condition Clearing ...................................... 40 Fail-Safe Detection .................................................... 40 Fail-Safe Operation .................................................... 40 Reset or Wake-up from Sleep .................................... 40 Fast Register Stack ............................................................ 68 Firmware Instructions ....................................................... 315 Flash Program Memory ...................................................... 89 Associated Registers ................................................. 97 Control Registers ....................................................... 90 EECON1 and EECON2 ..................................... 90 TABLAT (Table Latch) Register ......................... 92 TBLPTR (Table Pointer) Register ...................... 92 Erase Sequence ........................................................ 94 Erasing ....................................................................... 94 Operation During Code-Protect ................................. 97 Reading ...................................................................... 93 Table Pointer Boundaries Based on Operation ........................ 92 Table Pointer Boundaries .......................................... 92 Table Reads and Table Writes .................................. 89 Write Sequence ......................................................... 95 Writing To ................................................................... 95 Protection Against Spurious Writes ................... 97 Unexpected Termination .................................... 97 Write Verify ........................................................ 97 G General Call Address Support ......................................... 218 GOTO ............................................................................... 336 H Hardware Multiplier .......................................................... 105 Introduction .............................................................. 105 Operation ................................................................. 105 Performance Comparison ........................................ 105 High/Low-Voltage Detect ................................................. 293 Applications .............................................................. 297 Associated Registers ............................................... 297 Characteristics ......................................................... 382 Current Consumption ............................................... 295 Effects of a Reset .................................................... 297 Operation ................................................................. 294 During Sleep .................................................... 297 Setup ....................................................................... 295 Start-up Time ........................................................... 295 Typical Application ................................................... 297 HLVD. See High/Low-Voltage Detect. ............................. 293 HLVDCON Register ......................................................... 293 I I/O Ports ........................................................................... 121 I2C Associated Registers ............................................... 235 I2C Mode (MSSP) Acknowledge Sequence Timing .............................. 228 Baud Rate Generator .............................................. 221 Bus Collision During a Repeated Start Condition .................. 232 During a Stop Condition .................................. 234 Clock Arbitration ...................................................... 222 Clock Stretching ....................................................... 214 10-Bit Slave Receive Mode (SEN = 1) ............ 214 10-Bit Slave Transmit Mode ............................ 214 7-Bit Slave Receive Mode (SEN = 1) .............. 214 7-Bit Slave Transmit Mode .............................. 214 Clock Synchronization and the CKP bit (SEN = 1) .. 215 Effects of a Reset .................................................... 229 General Call Address Support ................................. 218 I2C Clock Rate w/BRG ............................................. 221 Master Mode ............................................................ 219 Operation ......................................................... 220 Reception ........................................................ 225 Repeated Start Condition Timing .................... 224 Start Condition Timing ..................................... 223 Transmission ................................................... 225 Multi-Master Communication, Bus Collision and Arbitration ................................................. 229 Multi-Master Mode ................................................... 229 Operation ................................................................. 207 Read/Write Bit Information (R/W Bit) ............... 207, 208 Registers ................................................................. 202 Serial Clock (RC3/SCK/SCL) ................................... 208 Slave Mode .............................................................. 207 Addressing ....................................................... 207 Reception ........................................................ 208 Transmission ................................................... 208 Sleep Operation ....................................................... 229 Stop Condition Timing ............................................. 228 ID Locations ............................................................. 299, 313 INCF ................................................................................ 336 INCFSZ ............................................................................ 337 In-Circuit Debugger .......................................................... 313 In-Circuit Serial Programming (ICSP) ...................... 299, 313 Indexed Literal Offset Addressing and Standard PIC18 Instructions ............................. 362 Indexed Literal Offset Mode ............................................. 362 Indirect Addressing ............................................................ 84 INFSNZ ............................................................................ 337 Initialization Conditions for all Registers ...................... 59–62 Instruction Cycle ................................................................ 69 Clocking Scheme ....................................................... 69 Instruction Flow/Pipelining ................................................. 69 Instruction Set .................................................................. 315 ADDLW .................................................................... 321 |
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