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PIC18F23K20-E/ML Datasheet(PDF) 445 Page - Microchip Technology |
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PIC18F23K20-E/ML Datasheet(HTML) 445 Page - Microchip Technology |
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445 / 456 page  2010 Microchip Technology Inc. DS41303G-page 445 PIC18F2XK20/4XK20 CONFIG6L Register ......................................................... 305 CONFIG7H Register ........................................................ 306 CONFIG7L Register ......................................................... 306 Configuration Bits ............................................................. 300 Configuration Register Protection .................................... 313 Context Saving During Interrupts ..................................... 119 CPFSEQ .......................................................................... 332 CPFSGT .......................................................................... 333 CPFSLT ........................................................................... 333 Customer Change Notification Service ............................ 453 Customer Notification Service .......................................... 453 Customer Support ............................................................ 453 CVREF Voltage Reference Specifications ........................ 381 D Data Addressing Modes ..................................................... 83 Comparing Addressing Modes with the Extended Instruction Set Enabled ..................... 86 Direct .......................................................................... 83 Indexed Literal Offset ................................................. 85 Instructions Affected .......................................... 85 Indirect ....................................................................... 83 Inherent and Literal .................................................... 83 Data EEPROM Code Protection ....................................................... 313 Data EEPROM Memory ..................................................... 99 Associated Registers ............................................... 103 EEADR and EEADRH Registers ............................... 99 EECON1 and EECON2 Registers ............................. 99 Operation During Code-Protect ............................... 102 Protection Against Spurious Write ........................... 102 Reading .................................................................... 101 Using ........................................................................ 102 Write Verify .............................................................. 101 Writing ...................................................................... 101 Data Memory ..................................................................... 71 Access Bank .............................................................. 77 and the Extended Instruction Set ............................... 85 Bank Select Register (BSR) ....................................... 71 General Purpose Registers ........................................ 77 Map for PIC18F23K20/43K20 .................................... 72 Map for PIC18F24K20/44K20 .................................... 73 Map for PIC18F25K20/45K20 .............................. 74, 75 Special Function Registers ........................................ 77 DAW ................................................................................. 334 DC and AC Characteristics Graphs and Tables .................................................. 403 DC Characteristics Input/Output ............................................................. 377 Peripheral Supply Current ........................................ 376 Power-Down Current ............................................... 371 Primary Idle Supply Current ..................................... 374 Primary Run Supply Current .................................... 374 RC Idle Supply Current ............................................ 373 RC Run Supply Current ........................................... 372 Secondary Oscillator Supply Current ....................... 375 Supply Voltage ......................................................... 371 DCFSNZ .......................................................................... 335 DECF ............................................................................... 334 DECFSZ ........................................................................... 335 Development Support ...................................................... 365 Device Differences ........................................................... 442 Device Overview ................................................................ 11 Details on Individual Family Members ....................... 12 New Core Features .................................................... 11 Other Special Features .............................................. 12 Device Reset Timers ......................................................... 55 PLL Lock Time-out .................................................... 55 Power-up Timer (PWRT) ........................................... 55 Time-out Sequence ................................................... 55 DEVID1 Register ............................................................. 307 DEVID2 Register ............................................................. 307 Direct Addressing .............................................................. 84 E ECCPAS Register ............................................................ 183 EECON1 Register ...................................................... 91, 100 Effect on Standard PIC Instructions ................................. 362 Effects of Power Managed Modes on Various Clock Sources ........................................................... 36 Effects of Reset PWM mode .............................................................. 152 Electrical Characteristics ................................................. 369 Enhanced Capture/Compare/PWM (ECCP) .................... 173 Associated Registers ............................................... 191 Capture and Compare Modes ................................. 174 Capture Mode. See Capture (ECCP Module). Enhanced PWM Mode ............................................. 175 Auto-Restart .................................................... 184 Auto-shutdown ................................................ 183 Direction Change in Full-Bridge Output Mode ............................................ 181 Full-Bridge Application ..................................... 179 Full-Bridge Mode ............................................. 179 Half-Bridge Application .................................... 178 Half-Bridge Application Examples ................... 185 Half-Bridge Mode ............................................. 178 Output Relationships (Active-High and Active-Low) .............................................. 176 Output Relationships Diagram ......................... 177 Programmable Dead Band Delay .................... 185 Shoot-through Current ..................................... 185 Start-up Considerations ................................... 182 Outputs and Configuration ....................................... 174 Standard PWM Mode .............................................. 174 Timer Resources ..................................................... 174 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................. 237 Errata ................................................................................. 10 EUSART .......................................................................... 237 Asynchronous Mode ................................................ 239 12-bit Break Transmit and Receive ................. 256 Associated Registers, Receive ........................ 245 Associated Registers, Transmit ....................... 241 Auto-Wake-up on Break .................................. 254 Baud Rate Generator (BRG) ........................... 249 Clock Accuracy ................................................ 246 Receiver .......................................................... 242 Setting up 9-bit Mode with Address Detect ..... 244 Transmitter ...................................................... 239 Baud Rate Generator (BRG) Associated Registers ....................................... 249 Auto Baud Rate Detect .................................... 253 Baud Rate Error, Calculating ........................... 249 Baud Rates, Asynchronous Modes ................. 250 Formulas .......................................................... 249 High Baud Rate Select (BRGH Bit) ................. 249 Clock polarity Synchronous Mode .......................................... 257 Data polarity Asychronous Receive ...................................... 242 Asychronous Transmit ..................................... 239 |
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