PIC18F47J53-ESLASHML datasheet(49/586 Pages) MICROCHIP

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 2010 Microchip Technology Inc.

Preliminary

DS39964B-page 49

PIC18F47J53 FAMILY

4.2

Run Modes

In the Run modes, clocks to both the core and

peripherals are active. The difference between these

modes is the clock source.

4.2.1

PRI_RUN MODE

The PRI_RUN mode is the normal, full-power execu-

tion mode of the microcontroller. This is also the default

mode upon a device Reset unless Two-Speed Start-up

is enabled (see Section 28.4 “Two-Speed Start-up”

for details). In this mode, the OSTS bit is set (see

Section 3.5.1 “Oscillator Control Register”).

4.2.2

SEC_RUN MODE

The SEC_RUN mode is the compatible mode to the

“clock switching” feature offered in other PIC18

devices. In this mode, the CPU and peripherals are

clocked from the Timer1 oscillator. This gives users the

option of low-power consumption while still using a

high-accuracy clock source.

SEC_RUN mode is entered by setting the SCS<1:0>

bits to ‘01’. The device clock source is switched to the

Timer1 oscillator (see Figure 4-1), the primary

oscillator

shut

down,

the

SOSCRUN

bit

(OSCCON2<6>) is set and the OSTS bit is cleared.

On transitions from SEC_RUN mode to PRI_RUN

mode, the peripherals and CPU continue to be clocked

from the Timer1 oscillator while the primary clock is

started. When the primary clock becomes ready, a

clock switch back to the primary clock occurs (see

Figure 4-2). When the clock switch is complete, the

SOSCRUN bit is cleared, the OSTS bit is set and the

primary clock would be providing the clock. The IDLEN

and SCS bits are not affected by the wake-up; the

Timer1 oscillator continues to run.

FIGURE 4-1:

TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE

FIGURE 4-2:

TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)

Note:

The Timer1 oscillator should already be

running prior to entering SEC_RUN mode.

If the T1OSCEN bit is not set when the

SCS<1:0> bits are set to ‘01’, entry to

SEC_RUN mode will not occur. If the

Timer1 oscillator is enabled, but not yet

running, device clocks will be delayed until

the oscillator has started. In such situa-

tions, initial oscillator operation is far from

stable and unpredictable operation may

result.

OSC1

Peripheral

Program

T1OSI

Counter

Clock

CPU

Clock

PC + 2

n-1

Clock Transition

PC + 4

Q3 Q4

OSC1

Peripheral

Program

T1OSI

PLL Clock

PC + 4

Output

CPU Clock

PC + 2

Clock

Counter

Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

SCS<1:0> Bits Changed

TPLL(1)

n-1 n

Clock

OSTS Bit Set

Transition

TOST(1)

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