HCS12 datasheet(282/452 Pages) FREESCALE

282 / 452 page

Instruction Glossary

S12CPUV2 Reference Manual, Rev. 4.0

282

Freescale Semiconductor

Operation:

(SP) – $0002

⇒ SP; RTNH : RTNL ⇒ (M(SP) : M(SP+1))

(SP) – $0002

⇒ SP; YH : YL ⇒ (M(SP) : M(SP+1))

(SP) – $0002

⇒ SP; XH : XL ⇒ (M(SP) : M(SP+1))

(SP) – $0002

⇒ SP; B : A⇒ (M(SP) : M(SP+1))

(SP) – $0001

⇒ SP; CCR ⇒ (M(SP))

Stop All Clocks

Description:

When the S control bit is set, STOP is disabled and operates like a 2-cycle

NOP instruction. When the S bit is cleared, STOP stacks CPU context,

stops all system clocks, and puts the device in standby mode.

Standby operation minimizes system power consumption. The contents of

registers and the states of I/O pins remain unchanged.

Asserting the RESET, XIRQ, or IRQ signals ends standby mode. Stacking

on entry to STOP allows the CPU to recover quickly when an interrupt is

used, provided a stable clock is applied to the device. If the system uses a

clock reference crystal that also stops during low-power mode, crystal

startup delay lengthens recovery time.

If XIRQ is asserted while the X mask bit = 0 (XIRQ interrupts enabled),

execution resumes with a vector fetch for the XIRQ interrupt. If the X mask

bit = 1 (XIRQ interrupts disabled), a 2-cycle recovery sequence including an

O cycle is used to adjust the instruction queue and the stack-pointer, and

execution continues with the next instruction after STOP.

STOP

Stop Processing

STOP

CCR Details:

HIN

––––––––

Source Form

Address

Mode

Object Code

Access Detail

HCS12

M68HC12

STOP (entering STOP)

INH

18 3E

OOSSSSsf

OOSSSfSs

(exiting STOP)

fVfPPP

(continue)

(if STOP disabled)

HCS12 Datasheet(PDF) 282 Page - Freescale Semiconductor, Inc

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