HCS12 datasheet(317/452 Pages) FREESCALE

317 / 452 page

S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

317

7.5.4 External Interrupts

External interrupt service requests are made by asserting an active-low

signal connected to the IRQ pin. Typically, control bits affect how the signal

is detected and recognized.

The I bit serves as the IRQ interrupt enable flag. When an IRQ interrupt is

recognized, the I bit is set to inhibit interrupts during the interrupt service

routine. Before other maskable interrupt requests can be recognized, the I

bit must be cleared. This is generally done by an RTI instruction at the end

of the service routine.

7.5.5 Return-from-Interrupt Instruction (RTI)

RTI is used to terminate interrupt service routines. RTI is an 8-cycle

instruction when no other interrupt is pending and 11 cycles (10 cycles in

M68HC12) when another interrupt is pending. In either case, the first five

cycles are used to restore (pull) the CCR, B:A, X, Y, and the return address

from the stack. If no other interrupt is pending at this point, three program

words are fetched to refill the instruction queue from the area of the return

address and processing proceeds from there.

If another interrupt is pending after registers are restored, a new vector is

fetched, and the stack pointer is adjusted to point at the CCR value that was

just recovered (SP = SP – 9). This makes it appear that the registers have

been stacked again. After the SP is adjusted, three program words are

fetched to refill the instruction queue, starting at the address the vector

points to. Processing then continues with execution of the instruction that is

now at the head of the queue.

7.6 Unimplemented Opcode Trap

The CPU12 has opcodes in all 256 positions in the page 1 opcode map, but

only 54 of the 256 positions on page 2 of the opcode map are used. If the

CPU attempts to execute one of the 202 unused opcodes on page 2, an

unimplemented opcode trap occurs. The 202 unimplemented opcodes are

essentially interrupts that share a common interrupt vector, $FFF8:$FFF9.

The CPU12 uses the next address after an unimplemented page 2 opcode

as a return address. This differs from the M68HC11 illegal opcode interrupt,

which uses the address of an illegal opcode as the return address. In the

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