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HCS12 Datasheet(PDF) 346 Page - Freescale Semiconductor, Inc |
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HCS12 Datasheet(HTML) 346 Page - Freescale Semiconductor, Inc |
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346 / 452 page ![]() S12CPUV2 Reference Manual, Rev. 4.0 346 Freescale Semiconductor are automatically updated by four and one so they point at the next membership function and fuzzy input respectively. Line 7 loads the current value of the next system input. Pointers in X and Y already point to the right places as a result of the automatic update function of the MEM instruction in line 5. Line 8 reloads a loop count. Lines 9 and 10 form a loop to fuzzify the seven labels of the second system input. When the program drops to line 11, the Y index register is pointing at the next location after the last fuzzy input, which is the first fuzzy output in this system. Line 11 sets the loop count to clear seven fuzzy outputs. Lines 12 and 13 form a loop to clear all fuzzy outputs before rule evaluation starts. Line 14 initializes the X index register to point at the first element in the rule list for the REV instruction. Line 15 initializes the Y index register to point at the fuzzy inputs and outputs in the system. The rule list (for REV) consists of 8-bit offsets from this base address to particular fuzzy inputs or fuzzy outputs. The special value $FE is interpreted by REV as a marker between rule antecedents and consequents. Line 16 initializes the A accumulator to the highest 8-bit value in preparation for finding the smallest fuzzy input referenced by a rule antecedent. The LDAA #$FF instruction also clears the V-bit in the CPU12’s condition code register so the REV instruction knows it is processing antecedents. During rule list processing, the V bit is toggled each time an $FE is detected in the list. The V bit indicates whether REV is processing antecedents or consequents. Line 17 is the REV instruction, a self-contained loop to process successive elements in the rule list until an $FF character is found. For a system of 17 rules with two antecedents and one consequent each, the REV instruction takes 259 cycles, but it is interruptible so it does not cause a long interrupt latency. Lines 18 through 20 set up pointers and an iteration count for the WAV instruction. |
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