HCS12 datasheet(365/452 Pages) FREESCALE

365 / 452 page

S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

365

9.6.2 WAV Interrupt Details

The WAV instruction includes a 7-cycle processing loop for each label of the

system output (8 cycles in M68HC12). Within this loop, the CPU checks

whether a qualified interrupt request is pending. If an interrupt is detected,

the current values of the internal temporary registers for the 24-bit and 16-bit

sums are stacked, the CPU registers are stacked, and the interrupt is

serviced.

A special processing sequence is executed when an interrupt is detected

during a weighted average calculation. This exit sequence adjusts the PC

so that it points to the second byte of the WAV object code ($3C), before the

PC is stacked. Upon return from the interrupt, the $3C value is interpreted

as a wavr pseudo-instruction. The wavr pseudo-instruction causes the CPU

to execute a special WAV resumption sequence. The wavr recovery

sequence adjusts the PC so that it looks like it did during execution of the

original WAV instruction, then jumps back into the WAV processing loop. If

another interrupt occurs before the weighted average calculation finishes,

the PC is adjusted again as it was for the first interrupt. WAV can be

interrupted any number of times, and additional WAV instructions can be

executed while a WAV instruction is interrupted.

9.6.3 Cycle-by-Cycle Details for WAV and wavr

The WAV instruction is unusual in that the logic flow has two separate entry

points. The first entry point is the normal start of a WAV instruction. The

second entry point is used to resume the weighted average operation after

a WAV instruction has been interrupted. This recovery operation is called

the wavr pseudo-instruction.

Figure 9-12 is a flow diagram of the WAV instruction in the HCS12,

including the wavr pseudo-instruction. Figure 9-12 is a flow diagram of the

WAV instruction in the M68HC12, including the wavr pseudo-instruction.

Each rectangular box in these figures represents one CPU clock cycle.

Decision blocks and connecting arrows are considered to take no time at all.

The letters in the small rectangles in the upper left corner of the boxes

correspond to execution cycle codes (refer to Section 6. Instruction

Glossary for details). Lower case letters indicate a cycle where 8-bit or no

data is transferred. Upper case letters indicate cycles where 16-bit data

could be transferred.

The cycle-by-cycle description provided here refers to the HCS12 flow in

Figure 9-11. In terms of cycle-by-cycle bus activity, the $18 page select

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