PIC24F04KA201T-ISLASHST datasheet(57/224 Pages) MICROCHIP

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Preliminary

DS39937B-page 55

PIC24F04KA201 FAMILY

6.3

Brown-out Reset (BOR)

The PIC24F04KA201 family devices implement a BOR

circuit, which provides the user several configuration

and power-saving options. The BOR is controlled by

the <BORV1:BORV0> and (BOREN<1:0>) Configura-

tion bits (FPOR<6:5,1:0>). There are a total of four

BOR configurations, which are provided in Table 6.3.1.

The BOR threshold is set by the BORV<1:0> bits. If

BOR is enabled (any values of BOREN<1:0>, except

‘00’), any drop of VDD below the set threshold point will

reset the device. The chip will remain in BOR until VDD

rises above threshold.

If the Power-up Timer is enabled, it will be invoked after

VDD rises above the threshold; it, then, will keep the chip

in Reset for an additional time delay, TPWRT, if VDD drops

below the threshold while the power-up timer is running.

The chip goes back into a BOR and the Power-up Timer

will be initialized. Once VDD rises above the threshold,

the Power-up Timer will execute the additional time

delay.

BOR and the Power-up Timer are independently

configured. Enabling the BOR Reset does not

automatically enable the PWRT.

6.3.1

SOFTWARE ENABLED BOR

When BOREN<1:0> = 01, the BOR can be enabled or

disabled by the user in software. This is done with the

control bit, SBOREN (RCON<13>). Setting SBOREN

enables the BOR to function as previously described.

Clearing the SBOREN disables the BOR entirely. The

SBOREN bit operates only in this mode; otherwise, it is

read as ‘0’.

Placing BOR under software control gives the user the

additional flexibility of tailoring the application to its

environment without having to reprogram the device to

change the BOR configuration. It also allows the user

to tailor the incremental current that the BOR con-

sumes. While the BOR current is typically very small, it

may have some impact in low-power applications.

6.3.2

DETECTING BOR

When BOR is enabled, the BOR bit (RCON<1>) is

always reset to ‘1’ on any BOR or POR event. This

makes it difficult to determine if a BOR event has

occurred just by reading the state of BOR alone. A

more reliable method is to simultaneously check the

state of both POR and BOR. This assumes that the

POR and BOR bits are reset to ‘0’ in the software

immediately after any POR event. If the BOR bit is ‘1’

while POR is ‘0’, it can be reliably assumed that a BOR

event has occurred.

6.3.3

DISABLING BOR IN SLEEP MODE

When BOREN<1:0> = 10, BOR remains under hard-

ware control and operates as previously described.

However, whenever the device enters Sleep mode,

BOR is automatically disabled. When the device

returns to any other operating mode, BOR is

automatically re-enabled.

This mode allows for applications to recover from

brown-out situations, while actively executing code,

when the device requires BOR protection the most. At

the same time, it saves additional power in Sleep mode

by eliminating the small incremental BOR current.

6.3.4

DEEP SLEEP BOR (DSBOR)

Deep Sleep BOR is a very low-power BOR circuitry.

Due to low current consumption, accuracy may vary.

DSBOR occurs anywhere between 1.55V and 1.95V.

DSBOR is selected in configuration through the

BORV<1:0> (FPOR<6:5>) bits = 00.

DSBOR re-arms the POR anywhere between 1.55V

and 1.95V; however, below 1.55V, the POR is asserted.

Note:

Even when the BOR is under software

control, the BOR Reset voltage level is still

set by the BORV1:BORV0 Configuration

bits. It can not be changed in software.

Note:

Even when the device exits from Deep

Sleep mode, both the POR and BOR are

set.

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