MC68HC705P9CS datasheet(127/160 Pages) FREESCALE

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Serial Input/Output Port (SIOP)

I/O Registers

MC68HC705P9 — Rev. 4.0

Technical Data

MOTOROLA

Serial Input/Output Port (SIOP)

127

This clearable, read-only bit is automatically set if the SIOP data

writing the SIOP data register while a transmission is in progress

causes invalid data to be transmitted or read. Clear DCOL by reading

the SIOP status register with SPIF set and then accessing the SIOP

data register. Because the clearing sequence accesses the SIOP

data register, the sequence has to be completed before another

transmission starts or DCOL is set again.

To clear DCOL when SPIF is not set, turn off the SIOP by writing a

zero to SPE and then turn it back on by writing a one to SPE. Reset

clears DCOL.

1 = Invalid access of SDR

0 = Valid access of SDR

10.7.3 SIOP Data Register

The SIOP data register (SDR) is both the transmit data register and the

receive data register. To read or write the SIOP data register, the SPE

bit in the SIOP control register must be set.

With the SIOP configured for master mode, writing to the SIOP data

the SIOP data register overwrites the previous contents. Reading or

writing to the SIOP data register while a transmission is in progress can

cause invalid data to be transmitted or received.

$000C

Bit 7

54321

Bit 0

Read:

Bit 7

54321

Bit 0

Write:

Reset:

Unaffected by reset

Figure 10-8. SIOP Data Register (SDR)

Freescale Semiconductor, Inc.

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