MC68HC705P9CS datasheet(97/160 Pages) FREESCALE

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Computer Operating Properly Watchdog (COP)

Interrupts

MC68HC705P9 — Rev. 4.0

Technical Data

MOTOROLA

Computer Operating Properly Watchdog (COP)

8.4.3 Clearing the COP Watchdog

To clear the COP watchdog and prevent a COP reset, write a logic zero

to bit 0 (COPC) of the COP register at location $1FF0.

If the main program executes within the COP timeout period, the clearing

routine needs to be executed only once. If the main program takes

longer than the COP timeout period, the clearing routine must be

executed more than once.

NOTE:

Place the clearing routine in the main program and not in an interrupt

routine. Clearing the COP watchdog in an interrupt routine might prevent

COP watchdog timeouts even though the main program is not operating

properly.

8.5 Interrupts

The COP watchdog does not generate interrupts.

8.6 COP Register

The COP register is a write-only register that returns the contents of

EPROM location $1FF0 when read.

COPC — COP Clear

COPC is a write-only bit. Periodically writing a logic zero to COPC

prevents the COP watchdog from resetting the MCU. Reset clears the

COPC bit.

$1FF0

Bit 7

54321

Bit 0

Read:

Write:

COPC

Reset:

UUUUUUU

= Unimplemented

U = Unaffected

Figure 8-1. COP Register (COPR)

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