S5T8809

PLL FREQUENCY SYNTHESIZER FOR PAGE

6

FUNCTIONAL DESCTRIPTION

Figure 1. Rx. N - Counter Register Programming Timing

•

Programmable N-counter consists of 5-bits Swallow Counter, Dual modulars Prescaler and 11-bits Main

Counter (if [PBC = 0], than 13-bits Main Counter)

•

The Divide Ratio is;

N = (P + 1)

× S + P (M - S) = PM + S;

P = Dual Modular Prescaler (32)

S = 5-bits Swallow Counter value (0 ~ 31)

M = 11-bits (PBC = High, 32 ~ 2047) or 13-bits (PBC = Low, 32 ~ 8291)

N = Programmable N-Counter value (N > S)

•

The Main Counter can be controlled by PBC pin, when the PBC (pin 9) state set to Low, the Programmable

N-counter range will be extend to 262143

Table 1. N-Counter Register Program Scheme (19 bit)

Bit

Bit 18 (ND 17) ~ Bit 1 (ND 0)

Bit 0 (LSB)

Name

ND

PMC

Description

N-Counter Data (ND 17 ~ ND 0)

Program Mode Control

Function

18 Bit Program Data

PBC = 1 : 16 bits (ND 15 ~ ND 0) will be valid

PBC = 1 : 18 bits (ND 17 ~ ND 0) will be valid

0: N-Counter Program

1: Ref. R-Counter Program

PMC

DATA

N_Counter Divider Data ( ND17 ~ ND0 )

EN

CLK

MSB : 1’st INPUT

positive edge triggered

LSB

MSB

1

2

3

4

5

6

7

8

13

14

15

16

17

18

19

PMC = 0

→ 16/18 bit N_Counter