PLL FREQUENCY SYNTHESIZER FOR PAGER

S5T8809

7

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Ex 1) In case of 16-bits program [PBC = High], Fc = 325.300MHz, Multiplier = 4, Fin = 75.975MHz

[Fin Freq. / Ref. Frequ.] = 75.975MHz / 6.25kHz = 1256

NOTE: According to the above equation, 12156 / 32(P) = 379, and left = 28

that means, Swallow CNT value is “11100”, Main CNT value is “379”

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Ex 2) In case of 18-bits program [PBC = Low], Fin = 330MHz

[Fin Freq. / Ref. Freq.] = [330MHz / 6.25kHz] = 52800

NOTE: The PMC bit is program mode control bit, if [0], the N-counter will be enabled

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The Input Reference Frequency (X-tal Oscillator) will be divided by 1/8 Prescaler, and then divided by pre-

programmed R-counter value once more.

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Programmable R-Counter consists of Fixed 1/8 Prescaler, 13 / 15-bits Programmable Counter

When FRC = 0, Fixed 1/8 Prescaler and 13-bits counter (Min. Divide value: 5) are enabled

RD = 8, R = 40 (= 8

× 5) ~ 65528 [Multiple 8]

When FRC = 1, Fixed 1/8 Prescaler is disabled, but using 15-bits counter (Min. Divide value: 5)

Table 2. R-Counter Register Program Scheme (19 bits)

Bit

Bit 18 ~ Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

Name

RD

LDC

FRC

TEST 1

PMC

Description

Ref. R-Counter Data

Lock Detector

Control

Frequency of

Reference

Control

TEST mode

control

Program mode

control

Function

15 Bit Programmable

Ref. R-Counter

FRC = 0 : 13 bits (RD12 — RD0)

FRC = 1 : 15 bits (RD14 — RD0)

0: Disable

LD out

1: Enable

LD out

0: R_CNT div.

= 8

× RD

1: R_CNT div.

= RD (15bit)

Mainly for

the product

Test

0: ND Program

1: RD Program

0

0

1

0

1

1

1

1

1

0

1

1

1

1

0

0

0

MSB

LSB

2

10

2

0

2

5

2

0

Main CNT 11 - bits

Swallow CNT 5-bits

PMC bit

1

1

0

0

1

1

1

0

0

1

0

0

0

0

0

0

0

MSB

LSB

2

10

2

0

2

5

2

0

Main CNT 13 - bits

Swallow CNT 5-bits

PMC bit

0

0

2

17