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PIC18F23K22-E/ML Datasheet(PDF) 334 Page - Microchip Technology |
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PIC18F23K22-E/ML Datasheet(HTML) 334 Page - Microchip Technology |
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334 / 496 page ![]() PIC18(L)F2X/4XK22 DS41412C-page 334 Preliminary 2010 Microchip Technology Inc. FIGURE 20-1: DIVSRCLK BLOCK DIAGRAM FIGURE 20-2: SR LATCH SIMPLIFIED BLOCK DIAGRAM 3 SRCLK<2:0> Peripheral Clock DIVSRCLK Programmable SRCLK divider 1:4 to 1:512 Tosc 4-512 cycles ... SRCLK<2:0> = "001" 1:8 t0+4 t0 t0+8 t0+12 SRPS S R Q Q Note 1: If R = 1 and S = 1 simultaneously, Q = 0, Q = 1 2: Pulse generator causes a pulse width of 2 TOSC clock cycles. 3: Name denotes the connection point at the comparator output. Pulse Gen(2) SR Latch(1) SRQEN SRSPE SRSC2E SRSCKE DIVSRCLK SYNCC2OUT(3) SRSC1E SYNCC1OUT(3) SRPR Pulse Gen(2) SRRPE SRRC2E SRRCKE DIVSRCLK SYNCC2OUT(3) SRRC1E SYNCC1OUT(3) SRLEN SRNQEN SRLEN SRQ SRNQ SRI SRI |
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