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PIC18F23K22-E/ML Datasheet(PDF) 336 Page - Microchip Technology |
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PIC18F23K22-E/ML Datasheet(HTML) 336 Page - Microchip Technology |
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336 / 496 page ![]() PIC18(L)F2X/4XK22 DS41412C-page 336 Preliminary 2010 Microchip Technology Inc. REGISTER 20-2: SRCON1: SR LATCH CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SRSPE: SR Latch Peripheral Set Enable bit 1 = SRI pin status sets SR Latch 0 = SRI pin status has no effect on SR Latch bit 6 SRSCKE: SR Latch Set Clock Enable bit 1 = Set input of SR latch is pulsed with DIVSRCLK 0 = Set input of SR latch is not pulsed with DIVSRCLK bit 5 SRSC2E: SR Latch C2 Set Enable bit 1 = C2 Comparator output sets SR Latch 0 = C2 Comparator output has no effect on SR Latch bit 4 SRSC1E: SR Latch C1 Set Enable bit 1 = C1 Comparator output sets SR Latch 0 = C1 Comparator output has no effect on SR Latch bit 3 SRRPE: SR Latch Peripheral Reset Enable bit 1 = SRI pin resets SR Latch 0 = SRI pin has no effect on SR Latch bit 2 SRRCKE: SR Latch Reset Clock Enable bit 1 = Reset input of SR latch is pulsed with DIVSRCLK 0 = Reset input of SR latch is not pulsed with DIVSRCLK bit 1 SRRC2E: SR Latch C2 Reset Enable bit 1 = C2 Comparator output resets SR Latch 0 = C2 Comparator output has no effect on SR Latch bit 0 SRRC1E: SR Latch C1 Reset Enable bit 1 = C1 Comparator output resets SR Latch 0 = C1 Comparator output has no effect on SR Latch TABLE 20-2: REGISTERS ASSOCIATED WITH THE SR LATCH Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page SRCON0 SRLEN SRCLK<2:0> SRQEN SRNQEN SRPS SRPR 335 SRCON1 SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E 336 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 154 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 154 WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 155 Legend: Shaded bits are not used with this module. |
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