PIC18F23K22-ESLASHML datasheet(335/496 Pages) MICROCHIP

335 / 496 page

 2010 Microchip Technology Inc.

Preliminary

DS41412C-page 335

PIC18(L)F2X/4XK22

TABLE 20-1:

DIVSRCLK FREQUENCY TABLE

SRCLK<2:0>

Divider

FOSC = 20 MHz

FOSC = 16 MHz

FOSC = 8 MHz FOSC = 4 MHz

FOSC = 1 MHz

111

512

25.6

s32 s64 s

128

s

512

s

110

256

12.8

s16 s32 s64 s

256

s

101

128

6.4

s8 s16 s32 s

128

s

100

3.2

s4 s8 s16 s64 s

011

1.6

s2 s4 s8 s32 s

010

0.8

s1 s2 s4 s16 s

001

80.4

s0.5 s1 s2 s8 s

000

40.2

s0.25 s0.5 s1 s4 s

SRCON0: SR LATCH CONTROL REGISTER

R/W-0

SRLEN

SRCLK<2:0>

SRQEN

SRNQEN

SRPS

SRPR

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented

C = Clearable only bit

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

SRLEN: SR Latch Enable bit(1)

1 = SR latch is enabled

0 = SR latch is disabled

bit 6-4

SRCLK<2:0>: SR Latch Clock Divider Bits

000 = Generates a 2 TOSC wide pulse on DIVSRCLK every 4 peripheral clock cycles

001 = Generates a 2 TOSC wide pulse on DIVSRCLK every 8 peripheral clock cycles

010 = Generates a 2 TOSC wide pulse on DIVSRCLK every 16 peripheral clock cycles

011 = Generates a 2 TOSC wide pulse on DIVSRCLK every 32 peripheral clock cycles

100 = Generates a 2 TOSC wide pulse on DIVSRCLK every 64 peripheral clock cycles

101 = Generates a 2 TOSC wide pulse on DIVSRCLK every 128 peripheral clock cycles

110 = Generates a 2 TOSC wide pulse on DIVSRCLK every 256 peripheral clock cycles

111 = Generates a 2 TOSC wide pulse on DIVSRCLK every 512 peripheral clock cycles

bit 3

SRQEN: SR Latch Q Output Enable bit

1 = Q is present on the SRQ pin

0 = Q is internal only

bit 2

SRNQEN: SR Latch Q Output Enable bit

1 =Q is present on the SRNQ pin

0 =Q is internal only

bit 1

SRPS: Pulse Set Input of the SR Latch bit(2)

1 = Pulse set input for 2 TOSC clock cycles

0 = No effect on set input

bit 0

SRPR: Pulse Reset Input of the SR Latch bit(2)

1 = Pulse reset input for 2 TOSC clock cycles

0 = No effect on Reset input

Note 1:

Changing the SRCLK bits while the SR latch is enabled may cause false triggers to the set and Reset

inputs of the latch.

Set only, always reads back ‘0’.

PIC18F23K22-E/ML Datasheet(PDF) 335 Page - Microchip Technology

PIC18F23K22-E/ML Datasheet(HTML) 335 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL