ISL97635 datasheet(18/28 Pages) INTERSIL

18 / 28 page

FN6434.2

December 22, 2008

Write Byte

The Write Byte protocol is only three bytes long. The first byte

starts with the slave address followed by the “command code,”

which translates to the “register index” being written. The third

byte contains the data byte that must be written into the register

selected by the “command code”. A shaded label is used on

cycles during which the slaved backlight controller “owns” or

“drives” the Data line. All other cycles are driven by the “host

master.”

Read Byte

As shown in the Figure 21, the four byte long Read Byte

protocol starts out with the slave address followed by the

“command code” which translates to the “register index.”

Subsequently, the bus direction turns around with the

re-broadcast of the slave address with bit 0 indicating a read

(“R”) cycle. The fourth byte contains the data being returned

by the backlight controller. That byte value in the data byte

reflects the value of the register being queried at the

“command code” index. Note the bus directions, which are

highlighted by the shaded label that is used on cycles during

which the slaved backlight controller “owns” or “drives” the

Data line. All other cycles are driven by the “host master.”

Slave Device Address

The slave address contains 7 MSB plus one LSB as R/W bit,

but these 8 bits are usually called Slave Aaddress bytes. As

shown in Figure 22, the high nibble of the Slave Address byte is

0x5 or 0101b to denote the “backlight controller class.” Bit 3 in

the lower nibble of the Slave Address byte is 1. Bit 0 is always

the R/W bit, as specified by the SMBus protocol. Note: In this

document, the device address will always be expressed as a

full 8-bit address instead of the shorter 7-bit address typically

used in other backlight controller specifications to avoid

confusion. Therefore, if the device is in the write mode where bit

0 is 0, the slave address byte is 0x58 or 01011000b. If the

device is in the read mode where bit 0 is 1, the slave address

byte is 0x59 or 01011001b.

The backlight controller may sense the state of the pins at POR

or during normal operation—the pins will not change state while

the device is in operation.

SMBus Register Definitions

The backlight controller registers are Byte wide and

accessible via the SMBus Read/Write Byte protocols. Their

bit assignments are provided in the following sections with

reserved bits containing a default value of “0”.

FIGURE 22. SLAVE ADDRESS BYTE DEFINITION

DEVICE

IDENTIFIER

DEVICE

ADDRESS

MSB

LSB

101100

R/W

TABLE 2A. REGISTER LISTING

ADDRESS

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

DEFAULT

VALUE

SMBUS

PROTOCOL

0x00

PWM

Brightness

Control Register

BRT7

BRT6

BRT5

BRT4

BRT3

BRT2

BRT1

BRT0

0xFF

Read and Write

0x01

Device Control

Reserved

PWM_MD

PWM_SEL

BL_CTL

0x00

Read and Write

0x02

Fault/Status

Reserved

2_CH_SD

1_CH_SD

BL_STAT

OV_CURR

THRM_SHDN

FAULT

0x00

Read Only

0x03

Identification

LED

PANEL

MFG3

MFG2

MFG1

MFG0

REV2

REV1

REV0

0xC8

Read Only

0x07

DC Brightness

Control Register

BRTDC7

BRTDC6

BRTDC5

BRTDC4

BRTDC3

BRTDC2

BRTDC1

BRTDC0

0xFF

Read and Write

0x08

Configuration

Reserved

FSW

VSC1

VSC0

0xXF

Read and Write

0x09

Output Channel

CH7

CH6

CH5

CH4

CH3

CH2

CH1

CH0

0xFF

Read and Write

ISL97635

ISL97635 Datasheet(PDF) 18 Page - Intersil Corporation

ISL97635 Datasheet(HTML) 18 Page - Intersil Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL