ISL97635 datasheet(23/28 Pages) INTERSIL

23 / 28 page

FN6434.2

December 22, 2008

DC Brightness Control Register (0x07)

The DC Brightness Control Register 0x07 allows users to

have additional dimming flexibility by:

1. Effectively achieving 16 bits of dimming control when DC

dimming is combined with PWM dimming or,

2. Achieving visual or audio noise free 8-bit DC dimming

over potentially noisy PWM dimming.

The bit assignment is shown in Figure 27. All of the bits in

this Register can be read or write. Steps 0 to 255 represent

the linear steps of current adjustment in DC on the fly. It can

also be considered as the peak current factory calibration

feature to account for various LED production batch

variations, but external EEPROM settings storing and

restoring are required.

• An SMBus Write Byte cycle to Register 0x07 sets the

brightness level in DC only.

• An SMBus Read Byte cycle to Register 0x07 returns the

current DC brightness level.

• Default value for Register 0x07 is 0xFF.

Configuration Register (0x08)

The Configuration Register allows users to set 2 levels of

channel Short-Circuit thresholds or disable it. It also allows

users to set the boost conversion switching frequency

between 1.2MHz and 600kHz.

The bit assignment is shown in Figure 28. The default value

for Register 0x08 is 0xFF

Output Channel Mask/Fault Readout Register

(0x09)

This register can be read or write; the bit position

corresponds to the channel. For example, bit 0 corresponds

to Ch0 and bit 6 corresponds to Ch6 and so on. Writing data

to this register, it enables the channels of interest. When

reading data from this register, any disabled channel and

any faulted out channel will read as 0. This allows the user to

determine which channel is faulty and optionally not enabling

it in order to allow the rest of the system to continue to

function. Additionally, a faulted out channel can be disabled

and re-enabled in order to allow a retry for any faulty channel

without having to power-down the other channels.

The bit assignment is shown in Figure 29. The default for

FIGURE 27. DESCRIPTIONS OF DC BRIGHTNESS CONTROL REGISTER

DC BRIGHTNESS CONTROL REGISTER

BRTDC7

BRTDC6

BRTDC5

BRTDC4

BRTDC3

BRTDC2

BRTDC1

BRTDC0

Bit 7 (R/W)

Bit 6 (R/W)

Bit 5 (R/W)

Bit 4 (R/W)

Bit 3 (R/W)

Bit 2 (R/W)

Bit 1 (R/W)

Bit 0 (R/W)

BIT ASSIGNMENT

BIT FIELD DEFINITIONS

BRTDC[7..0]

= 256 steps of DC brightness levels

CONFIGURATION REGISTER

RESERVED RESERVED RESERVED RESERVED RESERVED

FSW

VSC1

VSC0

Bit 7 (R/W)

Bit 6 (R/W)

Bit 5 (R/W)

Bit 4 (R/W)

Bit 3 (R/W)

Bit 2 (R/W)

Bit 1 (R/W)

Bit 0 (R/W)

BIT ASSIGNMENT

BIT FIELD DEFINITIONS

VSC[1..0]

2 levels of Short-Circuit Thresholds (1 = 8V, 0 = 3.1V, accuracy ±15%)

FSW[2]

2 levels of Switching Frequencies (1 = 1,200kHz, 0 = 600kHz)

FIGURE 28. DESCRIPTIONS OF CONFIGURATION REGISTER

ISL97635

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