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Chapter 3: Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet

Serial Configuration Device Memory Access

Configuration Handbook (Complete Two-Volume Set)

© December 2009

Altera Corporation

If the design must write more than 256 data bytes to the memory, it needs more than

one page of memory. Send the write enable and write bytes operation codes followed

by three new targeted address bytes and 256 data bytes before a new page is written.

nCS

must be driven high after the eighth bit of the last data byte has been latched in.

Otherwise, the device will not execute the write bytes operation. The write enable

latch bit in the status register is reset to 0 before the completion of each write bytes

operation. Therefore, the write enable operation must be carried out before the next

write bytes operation.

The device initiates the self-timed write cycle immediately after nCS is driven high.

respective EPCS devices. Therefore, you must account for this amount of delay before

another page of memory is written. Alternatively, you can check the status register’s

write in progress bit by executing the read status operation while the self-timed write

cycle is in progress. The write in progress bit is set to 1 during the self-timed write

cycle, and 0 when it is complete.

before write bytes operation is implemented. This can be achieved by either using the

erase sector instruction in a sector, or the erase bulk instruction throughout the entire

memory.

Erase Bulk Operation

The erase bulk operation code is b'1100 0111, with the MSB listed first. The erase

bulk operation sets all memory bits to 1 or 0xFF. Similar to the write bytes operation,

the write enable operation must be executed prior to the erase bulk operation so that

the write enable latch bit in the status register is set to 1.

You can implement the erase bulk operation by driving nCS low and then shifting in

the erase bulk operation code on the ASDI pin. nCS must be driven high after the

eighth bit of the erase bulk operation code has been latched in. Figure 3–16 shows the

timing diagram.

The device initiates the self-timed erase bulk cycle immediately after nCS is driven

respective EPCS devices.

Figure 3–15. Write Bytes Operation Timing Diagram (Note 1)

Notes to Figure 3–15:

(1) Use the erase sector or the erase bulk instruction to initialize the memory bytes of the serial configuration devices to all 1 or 0xFF before

implementing the write bytes operation.

(2) Address bit A[23] is a don't-care bit in EPCS64. Address bits A[23..21] are don't-care bits in EPCS16. Address bits A[23..19] are

don't-care bits in EPCS4. Address bits A[23..17] are don't-care bits in EPCS1.

(3) For .rpd files, write the LSB of the data byte first.

nCS

DCLK

ASDI

0

1

2

3

4

5

6

7

8

9

10

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

2072 2073 2074 2075 2076 2077 2078 2079

Operation Code

24-Bit Address (2)

23

22

21

3

2

1

0

765

4

MSB

MSB (3)

MSB (3)

MSB (3)

Data Byte 1

Data Byte 2

Data Byte 256

321

0

765

4

7

65

4

321

0

321

0