PIC24FJ64GA datasheet(208/262 Pages) MICROCHIP

208 / 262 page

PIC24FJ64GA004 FAMILY

DS39881C-page 206

Preliminary

23.3.1

WINDOWED OPERATION

The Watchdog Timer has an optional Fixed Window

mode of operation. In this Windowed mode, CLRWDT

instructions can only reset the WDT during the last 1/4

of the programmed WDT period. A CLRWDT instruction

executed before that window causes a WDT Reset,

similar to a WDT time-out.

Windowed WDT mode is enabled by programming the

WINDIS Configuration bit (CW1<6>) to ‘0’.

23.3.2

CONTROL REGISTER

The WDT is enabled or disabled by the FWDTEN

Configuration bit. When the FWDTEN Configuration bit

is set, the WDT is always enabled.

The WDT can be optionally controlled in software when

the FWDTEN Configuration bit has been programmed

to ‘0’. The WDT is enabled in software by setting the

SWDTEN control bit (RCON<5>). The SWDTEN

control bit is cleared on any device Reset. The software

WDT option allows the user to enable the WDT for

critical code segments and disable the WDT during

non-critical segments for maximum power savings.

FIGURE 23-2:

WDT BLOCK DIAGRAM

23.4

JTAG Interface

PIC24FJ64GA004 family devices implement a JTAG

interface, which supports boundary scan device testing

as well as in-circuit programming.

23.5

Program Verification and

Code Protection

For all devices in the PIC24FJ64GA004 family of

devices, the on-chip program memory space is treated

as a single block. Code protection for this block is

controlled by one Configuration bit, GCP. This bit

inhibits external reads and writes to the program

memory space. It has no direct effect in normal

execution mode.

Write protection is controlled by the GWRP bit in the

Configuration Word. When GWRP is programmed to

‘0’, internal write and erase operations to program

memory are blocked.

23.5.1

CONFIGURATION REGISTER

PROTECTION

The Configuration registers are protected against

inadvertent or unwanted changes or reads in two ways.

The primary protection method is the same as that of

the RP registers – shadow registers contain a compli-

mentary value which is constantly compared with the

actual value.

To safeguard against unpredictable events, Configura-

tion bit changes resulting from individual cell level

disruptions (such as ESD events) will cause a parity

error and trigger a device Reset.

The data for the Configuration registers is derived from

the Flash Configuration Words in program memory.

When the GCP bit is set, the source data for device

configuration is also protected as a consequence.

LPRC Input

WDT Overflow

Wake from Sleep

31 kHz

Prescaler

Postscaler

FWPSA

SWDTEN

FWDTEN

Reset

All Device Resets

Sleep or Idle Mode

LPRC Control

CLRWDT Instr.

PWRSAV Instr.

(5-bit/7-bit)

1:1 to 1:32.768

WDTPS3:WDTPS0

1 ms/4 ms

Exit Sleep or

Idle Mode

WDT

Counter

Transition to

New Clock Source

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