PCA85232DA datasheet(40/54 Pages) NXP

40 / 54 page

PCA85232

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Product data sheet

Rev. 1 — 8 December 2010

40 of 54

NXP Semiconductors

PCA85232

LCD driver for low multiplex rates

In the cascaded applications, the OSC pin of the PCA85232 with subaddress 0 is

connected to VSS so that this device uses its internal clock to generate a clock signal at

the CLK pin. The other PCA85232 devices are having the OSC pin connected to VDD,

meaning that these devices are ready to receive external clock, the signal being provided

by the device with subaddress 0.

In the case that the master is providing the clock signal to the slave devices, care must be

taken that the sending of display enable or disable will be received by both, the master

and the slaves at the same time. When the display is disabled the output from pin CLK is

disabled too. The disconnection of the clock may result in a DC component for the display.

Alternatively, the schematic can be also constructed such that all the devices have OSC

pin connected to VDD and thus an external CLK being provided for the system (all devices

connected to the same external CLK).

A configuration where SYNC is connected but all PCA85232 are using the internal clock

(OSC pin tied to VSS) is not recommended and may lead to display artifacts!

Table 21.

SYNC contact resistance

Number of devices

Maximum contact resistance

6000

3 to 5

2200

6 to 8

1200

PCA85232DA Datasheet(PDF) 40 Page - NXP Semiconductors