MM908E625ACEK datasheet(39/49 Pages) FREESCALE

39 / 49 page

Analog Integrated Circuit Device Data

Freescale Semiconductor

908E625

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Overtemperature Status Bit (HTF)

This read-only bit is a copy of the HTF bit in the Interrupt

Flag Register.

• 1 = Overtemperature condition has occurred

• 0 = No overtemperature condition has occurred

AUTONOMOUS WATCHDOG (AWD)

The Autonomous Watchdog module consists of three

functions:

• Watchdog function for the CPU in RUN mode

• Periodic interrupt function in STOP mode

• Cyclic wake-up function in STOP mode

The AWD is enabled if AWDIE, AWDRE, or AWDCC in the

AWDCTL Register is set. If these bits are cleared, the AWD

oscillator is disabled and the watchdog switched off.

WATCHDOG

The watchdog function is only available in RUN mode. On

setting the AWDRE bit, watchdog functionality in RUN mode

is activated. Once this function is enabled, it is not possible to

disable it via software.

If the timer reaches end value and AWDRE is set, a

system reset is initiated. Operations of the watchdog function

cease in STOP mode. Normal operation will be continued

when the system is back to RUN mode.

To prevent a watchdog reset, the watchdog timeout

counter must be reset before it reaches the end value. This is

done by a write to the AWDRST bit in the AWDCTL Register.

PERIODIC INTERRUPT

Periodic interrupt is only available in STOP mode. It is

enabled by setting the AWDIE bit in the AWDCTL Register. If

AWDIE is set, the AWD wakes up the system after a fixed

period of time. This time period can be selected with bit

AWDR in the AWDCTL Register.

CYCLIC WAKE-UP

The cyclic wake-up feature is only available in STOP

mode. If this feature is enabled, the selected Hall-effect

sensor input pins are switched on and sensed. If a “1” is

detected on one of these inputs and the interrupt for the Hall-

effect sensors is enabled, a system wake-up is performed.

(Switch on main voltage regulator and assert IRQ_A to the

microcontroller).

AUTONOMOUS WATCHDOG CONTROL

Autonomous Watchdog Reset Bit (AWDRST)

This write-only bit resets the Autonomous Watchdog

timeout period. AWDRST always reads 0. Reset clears

AWDRST bit.

• 1 = Reset AWD and restart timeout period

• 0 = No effect

Autonomous Watchdog Reset Enable Bit (AWDRE)

This read/write bit enables resets on AWD time-outs. A

reset on the RST_A is only asserted when the device is in

RUN mode. AWDRE is one-time setable (write once) after

each reset. Reset clears the AWDRE bit.

• 1 = Autonomous watchdog enabled

• 0 = Autonomous watchdog disabled

Autonomous Watchdog Interrupt Enable Bit (AWDIE)

This read/write bit enables CPU interrupts by the

Autonomous Watchdog timeout flag, AWFD. IRQ_A is only

asserted when the device is in STOP mode. Reset clears the

AWDIE bit.

• 1 = CPU interrupt requests from AWDF enabled

• 0 = CPU interrupt requests from AWDF disabled

Autonomous Watchdog Cyclic Check (AWDCC)

This read/write bit enables the cyclic check of the two-pin

Hall-effect sensor and the analog inputs. Reset clears the

AWDCC bit.

• 1 = Cyclic check of the Hall-effect sensor and analog

port

• 0 = No cyclic check of the Hall-effect sensor and analog

port

Autonomous Watchdog Timeout Flag Bit (AWDF)

This read/write flag is set when the Autonomous

Watchdog has timed out. Clear AWDF by writing a Logic [1]

to AWDF. Clearing AWDF also resets the AWD counter and

starts a new timeout period. Reset clears the AWDF bit.

Writing a Logic [0] to AWDF has no effect.

• 1 = AWD has timed out

• 0 = AWD has not yet timed out

Bits

Read

AWDR

AWDI

AWDC

AWDF

AWD

Write

AWDRS

Reset

MM908E625ACEK Datasheet(PDF) 39 Page - Freescale Semiconductor, Inc

MM908E625ACEK Datasheet(HTML) 39 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49

Datasheet Download

Link URL