MPC8315ECVRAGDA datasheet(38/112 Pages) FREESCALE

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MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0

Freescale Semiconductor

Ethernet: Three-Speed Ethernet, MII Management

9.5.4.2

SGMII Receive AC Timing Specifications

Table 38 provides the SGMII receive AC timing specifications. Source synchronous clocking is not

supported. Clock is recovered from the data. Figure 20 shows the SGMII Receiver Input Compliance

Mask eye diagram.

Table 38. SGMII Receive AC Timing Specifications

At recommended operating conditions with XCOREVDD = 1.0V ± 5%.

Parameter

Symbol

Min

Typ

Max

Unit

Notes

Deterministic Jitter Tolerance

0.37

—

UI p-p

Combined Deterministic and Random Jitter Tolerance

JDR

0.55

—

UI p-p

Sinusoidal Jitter Tolerance

JSIN

0.1

—

UI p-p

Total Jitter Tolerance

0.65

—

UI p-p

Bit Error Ratio

BER

—

10-12

—

Unit Interval

799.92

800

800.08

AC Coupling Capacitor

CTX

—

200

Notes:

1. Measured at receiver.

2. Each UI is 800 ps ± 100 ppm.

3. The external AC coupling capacitor is required. It’s recommended to be placed near the device transmitter outputs.

4. Refer to RapidIOTM 1x/4x LP Serial Physical Layer Specification for interpretation of jitter specifications.

MPC8315ECVRAGDA Datasheet(PDF) 38 Page - Freescale Semiconductor, Inc

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