MPC8315ECVRAGDA datasheet(70/112 Pages) FREESCALE

70 / 112 page

MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0

Freescale Semiconductor

PCI Express

and silicon. The RX eye diagram must be aligned in time using the jitter median to locate the center of the

eye diagram.

The eye diagram must be valid for any 250 consecutive UIs.

A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is

created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX

UI.

NOTE

The reference impedance for return loss measurements is 50. to ground for

both the D+ and D- line (that is, as measured by a Vector Network Analyzer

with 50. probes—see Figure 52). Note that the series capacitors, CPEACCTX,

are optional for the return loss measurement.

Figure 51. Minimum Receiver Eye Timing and Voltage Compliance Specification

16.5.1

Compliance Test and Measurement Load

The AC timing and voltage parameters must be verified at the measurement point, as specified within

0.2 inches of the package pins, into a test/measurement load shown in Figure 52.

NOTE

The allowance of the measurement point to be within 0.2 inches of the

package pins is meant to acknowledge that package/board routing may

benefit from D+ and D– not being exactly matched in length at the package

pin boundary.

VRX-DIFFp-p-MIN > 175 mV

0.4 UI = TRX-EYE-MIN

VRX-DIFF = 0 mV

(D+ D– Crossing Point)

VRX-DIFF = 0 mV

(D+ D– Crossing Point)

MPC8315ECVRAGDA Datasheet(PDF) 70 Page - Freescale Semiconductor, Inc