MPC8315ECVRAGDA datasheet(59/112 Pages) FREESCALE

59 / 112 page

MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0

Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

LVDS output driver features 50-

Ω termination resistor. It also assumes that the LVDS transmitter

establishes its own common mode level without relying on the receiver or other external component.

Figure 44. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only)

Figure 45 shows the SerDes reference clock connection reference circuits for LVPECL type clock driver.

Since LVPECL driver’s DC levels (both common mode voltages and output swing) are incompatible with

MPC8315E SerDes reference clock input’s DC requirement, AC-coupling has to be used. Figure 45

assumes that the LVPECL clock driver’s output impedance is 50

Ω. R1 is used to DC-bias the LVPECL

outputs prior to AC-coupling. Its value could be ranged from 140

Ω to 240Ω depending on clock driver

vendor’s requirement. R2 is used together with the SerDes reference clock receiver’s 50-

Ω termination

resistor to attenuate the LVPECL output’s differential peak level such that it meets the MPC8315E SerDes

reference clock’s differential input amplitude requirement (between 200mV and 800mV differential peak).

For example, if the LVPECL output’s differential peak is 900mV and the desired SerDes reference clock

input amplitude is selected as 600mV, the attenuation factor is 0.67, which requires R2 = 25

Ω. Please

consult clock driver chip manufacturer to verify whether this connection scheme is compatible with a

particular clock driver chip.

SD_REF_CLK

Clock Driver

100

Ω differential PWB trace

SerDes Refer.

CLK Receiver

Clock Driver

CLK_Out

LVDS CLK Driver Chip

10 nF

MPC8315E

MPC8315ECVRAGDA Datasheet(PDF) 59 Page - Freescale Semiconductor, Inc