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ADSP-BF504 Datasheet(PDF) 39 Page - Analog Devices

Part # ADSP-BF504
Description  Blackfin Embedded Processor
PDF  80 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADSP-BF504 Datasheet(HTML) 39 Page - Analog Devices

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Preliminary Technical Data
Rev. PrC
|
Page 39 of 80
|
January 2010
ADSP-BF504/F,ADSP-BF506F
Figure 18. Serial Ports
Table 30. Serial Ports—Enable and Three-State
Parameter
V
DDEXT=1.8 V
V
DDEXT=2.5/3.3 V
Min
Max
Min
Max
Unit
Switching Characteristics
tDTENE
Data Enable Delay from External TSCLKx1
0.0
0.0
ns
tDDTTE
Data Disable Delay from External TSCLKx1
10.0
10.0
ns
tDTENI
Data Enable Delay from Internal TSCLKx1
–2.0
–2.0
ns
tDDTTI
Data Disable Delay from Internal TSCLKx
1
3.0
3.0
ns
1 Referenced to drive edge.
Figure 19. Serial Ports — Enable and Three-State
tSDRI
RSCLKx
RFSx
DRx
DRIVE EDGE
tHDRI
tSFSI
tHFSI
tDFSI
tHOFSI
tSCLKIW
DATA RECEIVE—INTERNAL CLOCK
tSDRE
DATA RECEIVE—EXTERNAL CLOCK
RSCLKx
RFSx
DRx
tHDRE
tSFSE
tHFSE
tDFSE
tSCLKEW
tHOFSE
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RSCLKx OR TSCLKx CAN BE USED AS THE ACTIVE SAMPLING EDGE.
tDDTI
tHDTI
TSCLKx
TFSx
DTx
tSFSI
tHFSI
tSCLKIW
tDFSI
tHOFSI
DATA TRANSMIT—INTERNAL CLOCK
tDDTE
tHDTE
TSCLKx
TFSx
DTx
tSFSE
tDFSE
t SCLKEW
tHOFSE
DATA TRANSMIT—EXTERNAL CLOCK
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RSCLKx OR TSCLKx CAN BE USED AS THE ACTIVE SAMPLING EDGE.
SAMPLE EDGE
DRIVE EDGE
SAMPLE EDGE
DRIVE EDGE
SAMPLE EDGE
DRIVE EDGE
SAMPLE EDGE
tSCLKE
tSCLKE
tHFSE
TSCLKx
DTx
DRIVE
tDDTTE/I
tDTENE/I
DRIVE



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