ADSP-BF504 datasheet(51/80 Pages) AD

51 / 80 page

Preliminary Technical Data

Rev. PrC

Page 51 of 80

January 2010

ADSP-BF504/F,ADSP-BF506F

Output Enable Time Measurement

Output pins are considered to be enabled when they have made

a transition from a high impedance state to the point when they

start driving.

The output enable time t

ENA is the interval from the point when a

reference signal reaches a high or low voltage level to the point

when the output starts driving as shown on the right side of

Figure 46.

The time t

ENA

_MEASURED is the interval, from when the reference sig-

nal switches, to when the output voltage reaches V

TRIP(high) or

TRIP(low). For V

DDEXT (nominal) = 1.8V, VTRIP (high) is 1.05V,

and VTRIP (low) is 0.75V. For VDDEXT (nominal) = 2.5V, VTRIP

(high) is 1.5V and VTRIP (low) is 1.0V. For VDDEXT (nominal) =

3.3V, VTRIP (high) is 1.9V, and VTRIP (low) is 1.4V. Time tTRIP is

the interval from when the output starts driving to when the

output reaches the V

TRIP(high) or VTRIP(low) trip voltage.

Time t

ENA is calculated as shown in the equation:

If multiple pins are enabled, the measurement value is that of

the first pin to start driving.

Output Disable Time Measurement

Output pins are considered to be disabled when they stop driv-

ing, go into a high impedance state, and start to decay from their

output high or low voltage. The output disable time t

DIS is the

difference between t

DIS

_MEASURED and tDECAY as shown on the left side

of Figure 46.

The time for the voltage on the bus to decay by

ΔV is dependent

on the capacitive load C

L and the load current IL. This decay time

can be approximated by the equation:

The time t

DECAY is calculated with test loads CL and IL, and with

ΔV equal to 0.25 V for V

DDEXT (nominal) = 2.5 V/3.3 V and 0.15 V

for VDDEXT (nominal) = 1.8V.

The time t

DIS

_MEASURED is the interval from when the reference sig-

nal switches, to when the output voltage decays

ΔV from the

measured output high or output low voltage.

Example System Hold Time Calculation

To determine the data output hold time in a particular system,

first calculate t

DECAY using the equation given above. Choose

ΔV

to be the difference between the processor’s output voltage and

the input threshold for the device requiring the hold time. C

L is

the total bus capacitance (per data line), and I

L is the total leak-

age or three-state current (per data line). The hold time will be

DECAY plus the various output disable times as specified in the

Processor — Timing Specifications on Page 31.

Capacitive Loading

Output delays and holds are based on standard capacitive loads

of an average of 6 pF on all pins (see Figure 47). VLOAD is equal

to (VDDEXT) /2. The graphs of Figure 48 through Figure 55 show

how output rise time varies with capacitance. The delay and

hold specifications given should be derated by a factor derived

from these figures. The graphs in these figures may not be linear

outside the ranges shown.

Figure 46. Output Enable/Disable

REFERENCE

SIGNAL

tDIS

OUTPUT STARTS DRIVING

VOH (MEASURED)

VOL (MEASURED) + V

tDIS_MEASURED

VOH

(MEASURED)

VOL

(MEASURED)

VTRIP(HIGH)

VOH(MEASURED)

VOL(MEASURED)

HIGH IMPEDANCE STATE

OUTPUT STOPS DRIVING

tENA

tDECAY

tENA_MEASURED

tTRIP

VTRIP(LOW)

tENA

tENA_MEASURED tTRIP

–

tDIS

tDIS_MEASURED tDECAY

–

tDECAY

CL V

() I

⁄

Figure 47. Equivalent Device Loading for AC Measurements

(Includes All Fixtures)

Figure 48. Typical Rise and Fall Times (10%–90%) versus Load Capacitance

for Driver A at VDDEXT = Min

ZO = 50

(impedance)

TD = 4.04

1.18 ns

2pF

TESTER PIN ELECTRONICS

0.5pF

400

4pF

NOTES:

THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED

FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE

EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD), IS FOR

LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.

ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN

SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE

EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.

VLOAD

DUT

OUTPUT

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