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MPC5604B Datasheet(PDF) 2 Page - Freescale Semiconductor, Inc |
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MPC5604B Datasheet(HTML) 2 Page - Freescale Semiconductor, Inc |
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2 / 106 page ![]() MPC5604B/C Microcontroller Data Sheet, Rev. 8 Introduction Freescale Semiconductor 2 • Up to 4 serial communication interface (LINFlex) modules • Up to 6 enhanced full CAN (FlexCAN) modules with configurable buffers • 1 inter IC communication interface (I2C) module • Up to 123 configurable general purpose pins supporting input and output operations (package dependent) • Real Time Counter (RTC) with clock source from 128 kHz or 16 MHz internal RC oscillator supporting autonomous wakeup with 1 ms resolution with max timeout of 2 seconds • Up to 6 periodic interrupt timers (PIT) with 32-bit counter resolution • 1 System Module Timer (STM) • Nexus development interface (NDI) per IEEE-ISTO 5001-2003 Class Two Plus standard • Device/board boundary Scan testing supported with per Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1) • On-chip voltage regulator (VREG) for regulation of input supply for all internal levels 1 Introduction 1.1 Document overview This document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the device. To ensure a complete understanding of the device functionality, refer also to the device reference manual and errata sheet. 1.2 Description The MPC5604B/C is a family of next generation microcontrollers built on the Power Architecture® embedded category. The MPC5604B/C family of 32-bit microcontrollers is the latest achievement in integrated automotive application controllers. It belongs to an expanding family of automotive-focused products designed to address the next wave of body electronics applications within the vehicle. The advanced and cost-efficient host processor core of this automotive controller family complies with the Power Architecture embedded category and only implements the VLE (variable-length encoding) APU, providing improved code density. It operates at speeds of up to 64 MHz and offers high performance processing optimized for low power consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems and configuration code to assist with users implementations. |
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