MSC8154 datasheet(54/68 Pages) FREESCALE

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MSC8154 Quad-Core Digital Signal Processor Data Sheet, Rev. 2

Hardware Design Considerations

Freescale Semiconductor

3.1.2

Power-On Ramp Time

This section describes the AC electrical specification for the power-on ramp rate requirements for all voltage supplies (including

GVDD/SXPVDD/SXCVDD/QVDD/GVDD/NVDD, all VDD supplies, MVREF, and all AVDD supplies). Controlling the

power-on ramp time is required to avoid falsely triggering the ESD circuitry. Table 39 defines the power supply ramp time

specification.

3.1.3

Power Supply Guidelines

Use the following guidelines for power-up sequencing:

•

Couple M3VDD with the VDD power rail using an extremely low impedance path.

•

Couple inputs PLL1_AVDD, PLL2_AVDD and PLL3_AVDD with the VDD power rail using an RC filter (see Figure

37).

•

There is no dependency in power-on/power-off sequence between the GVDD1, GVDD2, NVDD, and QVDD power

rails.

•

Couple inputs M1VREF and M2VREF with the GVDD1 and GVDD2 power rails, respectively. They should rise at

the same time as or after their respective power rail.

•

There is no dependency between RapidIO supplies: SXCVDD1, SXCVDD2, SXPVDD1 and SXPVDD2 and other

MSC8154 supplies in the power-on/power-off sequence

•

Couple inputs SR1_PLL_AVDD and SR2_PLL_AVDD with SXCVDD1 and SXCVDD2 power rails, respectively,

using an RC filter (see Figure 38).

External voltage applied to any input line must not exceed the I/O supply voltage related to this line by more than 0.6 V at any

time, including during power-up. Some designs require pull-up voltages applied to selected input lines during power-up for

configuration purposes. This is an acceptable exception to the rule during start-up. However, each such input can draw up to

80 mA per input pin per MSC8154 device in the system during power-up. An assertion of the inputs to the high voltage level

before power-up should be with slew rate less than 4 V/ns.

The device power rails should rise in the following sequence:

VDD (and all coupled supplies)

After the above rails rise to 90% of their nominal voltage, the following I/O power rails may rise in any sequence (see

Figure 34): QVDD, NVDD, GVDD1, and GVDD2.

Table 39. Power Supply Ramp Rate

Parameter

Min

Max

Unit

Required ramp rate.

—

36000

V/s

Required ramp time.

µs

Notes:

Ramp time is specified as a linear ramp from 10% to 90% of nominal voltage of the specific voltage supply. If the ramp is

non-linear (for example, exponential), the maximum rate of change from 200 to 500 mV is the most critical because this range

might falsely trigger the ESD circuitry.

Required over the full recommended operating temperature range (see Table 3).

Figure 34. Supply Ramp-Up Sequence

VDD, MVDD, M3VDD

90%

NVDD, QVDD, GVDD1, GVDD2

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