MSC8154 datasheet(58/68 Pages) FREESCALE

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MSC8154 Quad-Core Digital Signal Processor Data Sheet, Rev. 2

Hardware Design Considerations

Freescale Semiconductor

3.4

SGMII AC-Coupled Serial Link Connection Example

Figure 39 shows an example of a 4-wire AC-coupled serial link connection. For additional layout suggestions, see AN3556

MSC815x High Speed Serial Interface Hardware Design Considerations, available on the Freescale website or from your local

sales office or representative.

3.5

Connectivity Guidelines

Note:

Although the package actually uses a ball grid array, the more conventional term pin is used to denote signal

connections in this discussion.

First, select the pin multiplexing mode to allocate the required I/O signals. Then use the guidelines presented in the following

subsections for board design and connections. The following conventions are used in describing the connectivity requirements:

GND indicates using a 10 k

Ω pull-down resistor (recommended) or a direct connection to the ground plane. Direct

connections to the ground plane may yield DC current up to 50 mA through the I/O supply that adds to overall power

consumption.

VDD indicates using a 10 kΩ pull-up resistor (recommended) or a direct connection to the appropriate power supply.

Direct connections to the supply may yield DC current up to 50 mA through the I/O supply that adds to overall power

consumption.

Mandatory use of a pull-up or pull-down resistor is clearly indicated as “pull-up/pull-down.” For buses, each pin on

the bus should have its own resistor.

NC indicates “not connected” and means do not connect anything to the pin.

The phrase “in use” indicates a typical pin connection for the required function.

Note:

Please see recommendations #1 and #2 as mandatory pull-down or pull-up connection for unused pins in case of

subset interface connection.

Figure 39. 4-Wire AC-Coupled SGMII Serial Link Connection Example

SGMII

SerDes Interface

Transmitter

SR[1–2]_TX[[1–2]

SR[1–2]_RX[1–2]

SR[1–2]_TX[1–2]

SR[1–2]_RX[1–2]

Receiver

CTX

SR[1–2]_RX[1–2]

SR[1–2]_RX[1–2]]

Receiver

Transmitter

SR[1–2]_TX[1–2

]

SR[1–2]_TX[1–2]

CTX

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