Baseband Signal Processor

FX829

© 1997 Consumer Microcircuits Limited

15

D/829/4

TXIDLEM

(Bit 5)

When this bit is "1", the TXIDLE interrupt will be gated out to the IRQN pin.

When this bit is "0", the TXIDLE interrupt will be inhibited. This bit has no effect on

the contents of the STATUS register.

RXDATAM

(Bit 4)

When this bit is "1", the RXDATA interrupt will be gated out to the IRQN pin.

When this bit is "0", the RXDATA interrupt will be inhibited. This bit has no effect

on the contents of the STATUS register.

TXDATAM

(Bit 3)

When this bit is "1", the TXDATA interrupt will be gated out to the IRQN pin.

When this bit is "0", the TXDATA interrupt will be inhibited. This bit has no effect

on the contents of the STATUS register.

RX SYNC

WORD PRIME

(Bit 2)

When this bit is set to "1", it enables the RX SYNC WORD detection.

It is cleared/disabled when a SYNC, SYNT, or RX SYNC WORD is detected.

It may also be cleared/disabled by writing "0" directly to this bit.

SYNT PRIME

(Bit 1)

When this bit is set to "1", it enables the SYNT detection.

It is cleared/disabled when a SYNC, SYNT, or RX SYNC WORD is detected.

It may also be cleared/disabled by writing "0" directly to this bit.

SYNC PRIME

(Bit 0)

When this bit is set to "1", it enables the SYNC detection.

It is cleared/disabled when a SYNC, SYNT, or RX SYNC WORD is detected.

It may also be cleared/disabled by writing "0" directly to this bit.

TXDATA Register (Hex Address $43)

This is the Tx data output register. It is double buffered, thus giving the user up to 8 bit periods to load in the

next 8 bits. FFSK data is transmitted immediately it is loaded if the transmitter is idle. Data is transmitted in 8-

bit bytes, bit 7 (MSB) will be transmitted first.