Baseband Signal Processor

FX829

© 1997 Consumer Microcircuits Limited

17

D/829/4

8-bit Read Only Registers

HEX

ADDRESS/

COMMAND

REGISTER

NAME

BIT 7

(D7)

BIT 6

(D6)

BIT 5

(D5)

BIT 4

(D4)

BIT 3

(D3)

BIT 2

(D2)

BIT 1

(D1)

BIT 0

(D0)

$41

STATUS

0

RXSUMF

TXIDLEF

RXDATAF

TXDATAF

RX SYNC

WORDF

SYNTF

SYNCF

$42

RXDATA

<--------------------------------------------- RXDATA --------------------------------------------->

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Read Only Register Description

STATUS Register (Hex address $41)

This register is used to indicate the status of the device as described below:

Bit 7

Not used, always set to zero.

RXSUMF

(Bit 6)

When this bit is "1", the Rx checksum is correct.

When this bit is "0", the Rx checksum is incorrect.

This bit is updated and latched in after reception of every eight bits (see CHKSUM

bit of the CONTROL2 register).

TXIDLEF

(Bit 5)

When all the Tx data and any checksum and one "hang-bit" have been transmitted,

this bit will be set to "1" to indicate that the transmitter is idle. This bit is reset to

"0" immediately after reading the STATUS register. When this bit is set to "1", an

interrupt may be generated depending on the state of the TXIDLEM bit in the

CONTROL 3 / IRQ ENABLE register.

RXDATAF

(Bit 4)

When a full byte of data is received and is available in the RXDATA register, this

bit will be set to "1". This bit is reset to "0" immediately after reading the STATUS

register. When this bit is set to "1" an interrupt may be generated depending on

the state of the RXDATAM bit in the CONTROL 3 / IRQ ENABLE register.

TXDATAF

(Bit 3)

When the Tx data buffer is empty this bit will be set to "1".

This bit is reset to "0" immediately after reading the STATUS register. When this

bit is set to "1", an interrupt may be generated depending on the state of the

TXDATAM bit in the CONTROL 3 / IRQ ENABLE register.

RX SYNC

WORDF

(Bit 2)

This bit is only defined when RX SYNC WORD PRIME is enabled.

When the data sequence specified in the RX SYNC WORD register has been

successfully matched to the Rx incoming data, this bit will be set to "1".

This bit is reset to "0" immediately after reading the STATUS register. When this

bit is set to "1", an interrupt will be generated, the checksum generator and byte

counter will be reset and SYNC PRIME, SYNT PRIME and RX SYNC WORD

PRIME will be reset.

SYNTF

(Bit 1)

This bit is only defined when SYNT PRIME is enabled.

When the data sequence specified by SYNT has been successfully matched to the

Rx incoming data, this bit will be set to "1".

This bit is reset to "0" immediately after reading the STATUS register. When this

bit is set to "1", an interrupt will be generated, the checksum generator and byte

counter will be reset and SYNC PRIME, SYNT PRIME and RX SYNC WORD

PRIME will be reset.