Baseband Signal Processor

FX829

© 1997 Consumer Microcircuits Limited

18

D/829/4

SYNCF

(Bit 0)

This bit is only defined when SYNC PRIME is enabled.

When the data sequence specified by SYNC has been successfully matched to the

Rx incoming data, this bit will be set to "1".

This bit is reset to "0" immediately after reading the STATUS register. When this

bit is set to "1", an interrupt will be generated, the checksum generator and byte

counter will be reset and SYNC PRIME, SYNT PRIME and RX SYNC WORD

PRIME will be reset.

RXDATA Register (Hex address $42)

This register contains the last byte of data received. It is updated every 8 bits at the same time as the

RXSUMF bit in the STATUS register is updated.

The RXDATA register is double buffered, thus giving the user up to 8 bit periods to read the data before it is

overwritten by the next byte.

1.5.2

FFSK Checksum Generation and Checking

Generation

The checksum generator takes the m x 8 bits from the m bytes of information, sequentially loaded into

the TXDATA register and divides them modulo-2, by the generating polynomial:

It then takes the 15-bit remainder from the polynomial divider, inverts the last bit and appends an

EVEN parity bit generated from the initial m x 8 bits and the 15-bit remainder (with the last bit

inverted).

This 16-bit word is used as the "CHECKSUM". See Figure 5.

(m = the number of bytes in the information to be sent)

Figure 5 Checksum Generation